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Timer Module Documentation

Overview

The axil_timer module provides a 64-bit programmable timer/counter accessible via an AXI-Lite interface. It supports basic timing, event counting, and cascading operations.

Features

  • 64-bit Timer (split into two 32-bit registers)
  • Configurable as Timer (clock cycle count) or Counter (external event count)
  • Direction control (Count Up / Count Down)
  • Cascading support for 64-bit operation
  • AXI-Lite slave interface for register access

Register Map

Offset Name Description Access
0x00 TIMER_LO Timer Low [31:0] R/W
0x04 TIMER_HI Timer High [63:32] R/W
0x08 TIMER_CTRL Timer Control Register R/W
0x0C TIMECMP_LO Compare Low [31:0] R/W
0x10 TIMECMP_HI Compare High [63:32] R/W

TIMER Registers (0x00, 0x04)

  • Write: Loads the timer/counter with a specific value.
  • Read: Returns the current value of the timer/counter.
  • Note: Writing to these registers updates the internal 32 bit counter after the next clock cycle.

TIMER_CTRL Register (0x08)

Bit Name Description
0 ENABLE 1: Enable Timer/Counter
0: Disable (Stop)
1 DIR 1: Count Up
0: Count Down
2 MODE 1: Counter Mode (External Event)
0: Timer Mode (Internal Clock)
3 IRQ_EN 1: Enable compare-match interrupt output
0: Interrupt gated off

TIMECMP Registers (0x0C, 0x10)

  • Write: Sets the 64-bit compare value (split across low and high registers).
  • Read: Returns the current compare value.
  • Default: 0xFFFFFFFF_FFFFFFFF on reset (no spurious interrupt on startup).

Compare-Match Interrupt

When IRQ_EN (TIMER_CTRL bit 3) is set, the timer_irq_o output asserts whenever {TIMER_HI, TIMER_LO} >= {TIMECMP_HI, TIMECMP_LO}. This output is wired to the CPU's mtip (Machine Timer Interrupt Pending) input.

To clear the interrupt, software should either:

  • Set TIMECMP to a value greater than the current timer value, or
  • Clear IRQ_EN in TIMER_CTRL.

Modes of Operation

Timer Mode (Mode = 0)

Increments or decrements on every clock cycle when enabled. Used for measuring time intervals or generating delays.

Counter Mode (Mode = 1)

Increments or decrements on the rising edge of the external event signal (ext_event_i). Used for counting external events like sensor pulses.

64-bit Cascading

The module automatically handles 64-bit cascading. The High timer increments/decrements only when the Low timer overflows/underflows, ensuring a seamless 64-bit value properly distributed across the two 32-bit registers.

Interface

AXI-Lite Slave

Standard AXI-Lite slave interface with:

  • 32-bit data bus
  • 12-bit address (4KB address space)

External Signals

input  wire ext_event_i   // External event input for Counter Mode
output wire timer_irq_o   // Compare-match interrupt output (active high)

Usage Examples

1. Basic Timer (Count Up)

// 1. Reset Timer Low and High
*(volatile uint32_t*)0x04002000 = 0;
*(volatile uint32_t*)0x04002004 = 0;

// 2. Enable Timer (Bit 0=1) + Count Up (Bit 1=1) + Timer Mode (Bit 2=0) -> 0x3
*(volatile uint32_t*)0x04002008 = 0x3;

2. Event Counter

// 1. Reset Timer
*(volatile uint32_t*)0x04002000 = 0;

// 2. Enable Counter (Bit 0=1) + Count Up (Bit 1=1) + Counter Mode (Bit 2=1) -> 0x7
*(volatile uint32_t*)0x04002008 = 0x7;

// 3. Read Count
uint32_t count = *(volatile uint32_t*)0x04002000;

Address Map in Z-Core System

Peripheral Base Address Size
Memory 0x00000000 64MB
UART 0x04000000 4KB
GPIO 0x04001000 4KB
Timer 0x04002000 4KB