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Convolution.cpp
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#include <ATen/ATen.h>
#include <ATen/Parallel.h>
#include <ATen/native/ConvUtils.h>
#include <ATen/native/Pool.h>
#include <ATen/native/cpu/DepthwiseConvKernel.h>
#include <ATen/native/utils/ParamUtils.h>
#include <ATen/native/xnnpack/Engine.h>
#include <ATen/NativeFunctions.h>
#include <c10/util/accumulate.h>
#include <c10/util/irange.h>
#include <ATen/Config.h>
#include <c10/macros/Macros.h>
#include <limits>
#if AT_NNPACK_ENABLED()
#include <nnpack.h>
#endif
constexpr int MIOPEN_DIM_MAX = 5;
namespace at { namespace native {
DEFINE_DISPATCH(convolution_depthwise3x3_winograd_stub);
struct ConvParams {
std::vector<int64_t> stride;
std::vector<int64_t> padding;
std::vector<int64_t> dilation;
bool transposed;
std::vector<int64_t> output_padding;
int groups;
bool benchmark;
bool deterministic;
bool cudnn_enabled;
bool allow_tf32;
bool is_strided() const;
bool is_dilated() const;
bool is_padded() const;
bool is_output_padding_neg() const;
bool is_output_padding_big() const;
bool is_padding_neg() const;
bool is_stride_nonpos() const;
void view1d_as_2d();
bool use_cpu_depthwise3x3_winograd(const at::Tensor& input, const at::Tensor& weight, const at::Tensor& bias) const;
bool needs_64bit_indexing_no_split(const at::Tensor& input, const at::Tensor& weight) const;
bool use_cudnn(const at::Tensor& input, const at::Tensor& weight) const;
bool use_cudnn_depthwise(const at::Tensor& input, const at::Tensor& weight) const;
bool use_miopen(const at::Tensor& input, const at::Tensor& weight, bool bias_defined) const;
bool use_mkldnn(const at::Tensor& input, const at::Tensor& weight) const;
bool use_nnpack(const at::Tensor& input, const at::Tensor& weight) const;
bool use_xnnpack(const at::Tensor& input, const at::Tensor& weight, const at::Tensor& bias) const;
bool is_depthwise(const at::Tensor& input, const at::Tensor& weight) const;
};
std::ostream& operator<<(std::ostream & out, const ConvParams& params) {
out << "ConvParams {"
<< " stride = " << IntArrayRef{params.stride}
<< " padding = " << IntArrayRef{params.padding}
<< " dilation = " << IntArrayRef{params.dilation}
<< " transposed = " << params.transposed
<< " output_padding = " << IntArrayRef{params.output_padding}
<< " groups = " << params.groups
<< " benchmark = " << params.benchmark
<< " deterministic = " << params.deterministic
<< " cudnn_enabled = " << params.cudnn_enabled
<< " allow_tf32 = " << params.allow_tf32
<< "}";
return out;
}
auto ConvParams::is_strided() const -> bool {
bool is_strided = false;
for (int s : stride) {
is_strided |= (s != 1);
}
return is_strided;
}
auto ConvParams::is_dilated() const -> bool {
bool is_dilated = false;
for (int d : dilation) {
is_dilated |= (d != 1);
}
return is_dilated;
}
auto ConvParams::is_padded() const -> bool {
bool is_padded = false;
for (int p : padding) {
is_padded |= (p != 0);
}
return is_padded;
}
auto ConvParams::is_output_padding_neg() const -> bool {
bool is_non_neg = false;
for (int p : output_padding) {
is_non_neg |= (p < 0);
}
return is_non_neg;
}
auto ConvParams::is_output_padding_big() const -> bool {
bool is_big = false;
for (size_t i = 0; i < output_padding.size(); i++) {
is_big |= (output_padding[i] >= stride[i]);
}
return is_big;
}
auto ConvParams::is_padding_neg() const -> bool {
bool is_non_neg = false;
for (int p : padding) {
is_non_neg |= (p < 0);
}
return is_non_neg;
}
auto ConvParams::is_stride_nonpos() const -> bool {
bool is_nonpos = false;
for (int s : stride) {
is_nonpos |= (s <= 0);
}
return is_nonpos;
}
auto ConvParams::view1d_as_2d() -> void {
if (stride.size() == 1) {
stride.insert(stride.begin(), 1);
padding.insert(padding.begin(), 0);
dilation.insert(dilation.begin(), 1);
output_padding.insert(output_padding.begin(), 0);
}
}
auto ConvParams::use_cpu_depthwise3x3_winograd(
const at::Tensor& input,
const at::Tensor& weight,
const at::Tensor& bias) const -> bool {
#if defined(__ARM_NEON__) && !defined(C10_IOS)
// Currently only 3x3 depthwise convolutions on tensors of float are supported.
return (input.ndimension() == 4) &&
(input.size(1) == groups) &&
(weight.ndimension() == 4 ) &&
(weight.size(0) % input.size(1) == 0) &&
(weight.size(2) == 3) &&
(weight.size(3) == 3) &&
(input.device().is_cpu()) &&
(input.scalar_type() == at::kFloat) &&
input.is_contiguous() &&
(weight.device().is_cpu()) &&
(weight.scalar_type() == at::kFloat) &&
weight.is_contiguous() &&
(!bias.defined() ||
((bias.device().is_cpu()) &&
(bias.scalar_type() == at::kFloat))) &&
!is_strided() &&
!is_dilated() &&
!transposed;
#else
return false;
#endif
}
auto ConvParams::needs_64bit_indexing_no_split(const at::Tensor& input, const at::Tensor& weight) const -> bool {
constexpr int64_t int_max = std::numeric_limits<int>::max();
int64_t numel_input = input.numel();
// empty input
if (numel_input == 0) {
return false;
}
// input size can not be reduced to the range of int by splitting the batch dim
int64_t n = input.size(0);
if (numel_input / n > int_max) {
return true;
}
// output size can not be reduced to the range of int by splitting the batch dim
int64_t outsize = 1;
if (transposed) {
std::vector<int64_t> o = conv_input_size(input.sizes(), weight.sizes(), padding, output_padding, stride, dilation, groups);
outsize = c10::multiply_integers(o.begin() + 1, o.end());
} else {
std::vector<int64_t> o = conv_output_size(input.sizes(), weight.sizes(), padding, stride, dilation);
outsize = c10::multiply_integers(o.begin() + 1, o.end());
}
return outsize > int_max;
}
auto ConvParams::use_cudnn(const at::Tensor& input, const at::Tensor& weight) const -> bool {
if (needs_64bit_indexing_no_split(input, weight)) {
return false;
}
if (!detail::getCUDAHooks().compiledWithCuDNN()) {
return false;
}
if (!input.is_cuda() || !cudnn_enabled) {
return false;
}
if (input.scalar_type() == at::kBFloat16 || weight.scalar_type() == at::kBFloat16) {
return false;
}
if (!cudnn_conv_use_channels_last(input, weight)) { // bypass dilation checks for channels-last convolution
if (deterministic && is_dilated()) {
// cudnn doesn't support deterministic dilated convolution fully yet
return false;
}
if (is_dilated()) {
return detail::getCUDAHooks().supportsDilatedConvolutionWithCuDNN() && !is_output_padding_big();
}
}
return !is_output_padding_big();
}
auto ConvParams::use_miopen(const at::Tensor& input, const at::Tensor& weight, bool bias_defined) const -> bool {
if (needs_64bit_indexing_no_split(input, weight)) {
return false;
}
return ((input.scalar_type() == at::kFloat) || (input.scalar_type() == at::kHalf) || (input.scalar_type() == at::kBFloat16))
&& detail::getCUDAHooks().compiledWithMIOpen()
&& input.is_cuda()
&& input.dim() <= MIOPEN_DIM_MAX
&& !(groups > 1 && is_dilated()) // MIOpen currently does not support dilation with groups of size > 1
&& !(input.scalar_type() == at::kBFloat16 && bias_defined) // MIOpen currently doesn't support bias with bfloat16
&& cudnn_enabled
;
}
auto ConvParams::use_mkldnn(const at::Tensor& input, const at::Tensor& weight) const -> bool {
#if AT_MKLDNN_ENABLED()
if (!at::globalContext().userEnabledMkldnn()) {
return false;
}
return (input.is_mkldnn()) || // input is mkldnn Tensor
(input.device().is_cpu() &&
input.scalar_type() == kFloat && // only on CPU Float Tensors
!transposed && // or transposed tensors
// For 1x1 filters, MKLDNN is faster than THNN when multi-threaded,
// but THNN is faster when single-threaded.
(is_strided() || is_dilated() || input.size(0) >= 16 ||
weight.size(-1) != 1 || weight.size(-2) != 1 || at::get_num_threads() > 1) &&
(groups > 1
|| (weight.size(-1) > 3 && weight.size(-2) > 3)
|| input.size(0) > 1
|| input.size(0)*input.size(1)*input.size(2)*input.size(3) > 20480) // for some case, native is faster
);
#endif
return false;
}
auto ConvParams::use_nnpack(const at::Tensor& input, const at::Tensor& weight) const -> bool {
#if AT_NNPACK_ENABLED()
return at::_nnpack_available() &&
input.device().is_cpu() &&
input.scalar_type() == kFloat && // only on CPU Float Tensors
!is_dilated() && // or dilation
!transposed && // or transposed tensors
input.ndimension() == 4 && // must be in NCHW format
weight.ndimension() == 4 &&
(weight.size(2) < 17) && (weight.size(3) < 17) // NNPACK only supports kernels up to 16x16
#if !defined(C10_MOBILE)
&& input.size(0) >= 16 // ensure large enough batch size to ensure perf, tuneable
#endif
;
#endif
return false;
}
auto ConvParams::use_xnnpack(
const at::Tensor& input,
const at::Tensor& weight,
const at::Tensor& bias) const -> bool {
#if defined(C10_MOBILE)
if (!transposed) {
return (input.size(1) == groups) &&
xnnpack::use_convolution2d(
input,
weight,
bias,
padding,
stride,
dilation,
groups,
transposed);
}
#endif
return false;
}
// We currently only have depthwise support for the case where groups ==
// nInputPlane and nInputPlane == nOutputPlane (the latter due to the lack of
// a depthwise multiplier)
auto ConvParams::is_depthwise(
const at::Tensor& input, const at::Tensor& weight) const -> bool {
return input.is_cuda() &&
!transposed &&
(input.ndimension() == 4 || input.ndimension() == 5) &&
input.size(1) == groups &&
groups > 1 && // no point if there is only a single group
weight.size(0) % input.size(1) == 0; // output channels must be a multiple of input channels
}
// Check workload to activate fast depthwise FP16 cudnn conv kernels
bool check_cudnn_depthwise_workload(const at::Tensor& input, int stride) {
int w = input.size(3); // same as h
int ch = input.size(1);
int bs = input.size(0);
if (stride==1) {
if (w >= 7) {
// All batch sizes and nb_channels
if (w >= 112) {
return true;
}
// large nb_channels
if (ch >= 1024) {
if (w >= 56) {
return true;
} else if (bs >= 32) {
return true;
}
}
// batch_size specific
if (bs >= 128) {
if (ch >= 512) {
return true;
} else if (ch >= 64) {
if (w >= 14) {
return true;
}
} else if ((ch >= 32) && (w >=28)) {
return true;
}
} else if (bs >= 64) {
if ((ch >= 256) && (w >= 14)) {
return true;
} else if ((ch >= 32) && (w >= 28)) {
return true;
}
} else if (bs >= 32) {
if ((ch >= 256) && (w >= 14)) {
return true;
} else if ((ch >= 128) && (w >= 28)) {
return true;
} else if ((ch >= 32) && (w >= 56)) {
return true;
}
} else if (bs >= 16) {
if ((ch >= 1024) && (w >= 14)) {
return true;
}
if ((ch >= 256) && (w >= 28)) {
return true;
} else if ((ch >= 32) && (w >= 56)) {
return true;
}
} else if (bs >= 8) {
if ((ch >= 512) && (w >= 28)) {
return true;
} else if ((ch >= 64) && (w >= 56)) {
return true;
}
}
}
} else if (stride==2) {
if (ch < 256) {
return false;
}
if (w >= 7) {
if (bs >= 128) {
if (ch >= 1024) {
return true;
} else if ((ch >= 512) && (w >= 14)) {
return true;
} else if (w >= 28) {
return true;
}
} else if (bs >= 64) {
if ((ch >= 512) && (w >= 14)) {
return true;
} else if (w >= 28) {
return true;
}
} else if (bs >= 32) {
if ((ch >= 1024) && (w >= 14)) {
return true;
} else if (w >= 28) {
return true;
}
} else if (bs >= 16) {
if ((ch >= 512) && (w >= 28)) {
return true;
} else if (w >= 56) {
return true;
}
} else if (bs >= 8) {
if ((ch >= 1024) && (w >= 28)) {
return true;
} else if (w >= 56) {
return true;
}
} else if (bs >= 1) {
if ((ch >= 512) && (w >=112)) {
return true;
}
}
}
}
return false;
}
// Use cudnn for FP16 depthwise convolutions
auto ConvParams::use_cudnn_depthwise(
const at::Tensor& input, const at::Tensor& weight) const -> bool {
if (cudnn_conv_use_channels_last(input, weight) && use_cudnn(input, weight)) {
return true;
}
if (detail::getCUDAHooks().supportsDepthwiseConvolutionWithCuDNN()) {
long cudnn_version = detail::getCUDAHooks().versionCuDNN();
bool kernel_cond = (cudnn_version >= 7600 &&
use_cudnn(input, weight) &&
input.scalar_type() == kHalf && // only for FP16
weight.scalar_type() == kHalf &&
is_depthwise(input, weight) &&
input.ndimension() == 4 && // TODO: 5-D contiguous depthwise is not supported yet, need benchmarks
weight.size(2) == weight.size(3) && // only square kernels
input.size(2) >= 7 && // min width/height 7
!is_dilated() && // no dilation supported
stride[0] == stride[1] && // equal strides
((weight.size(3) == 3) || (weight.size(3) == 1)) &&
input.size(1) >= 32); // min 32 channels supported)
if (kernel_cond) {
return check_cudnn_depthwise_workload(input, stride[0]);
} else {
return false;
}
} else {
return false;
}
}
static void check_shape_forward(const at::Tensor& input,
const c10::IntArrayRef& weight_sizes, const at::Tensor& bias,
const ConvParams& params) {
int64_t k = input.ndimension();
int64_t weight_dim = weight_sizes.size();
int64_t groups = params.groups;
auto padding = params.padding;
auto output_padding = params.output_padding;
auto stride = params.stride;
auto dilation = params.dilation;
bool transposed = params.transposed;
TORCH_CHECK(!params.is_padding_neg(), "negative padding is not supported");
TORCH_CHECK(!params.is_output_padding_neg(), "negative output_padding is not supported");
TORCH_CHECK(!params.is_stride_nonpos(), "non-positive stride is not supported");
TORCH_CHECK(weight_dim == k,
"Expected ", weight_dim, "-dimensional input for ", weight_dim,
"-dimensional weight ", weight_sizes, ", but got ", k, "-dimensional input of size ",
input.sizes(), " instead");
TORCH_CHECK(weight_sizes[0] >= groups,
"Given groups=", groups, ", expected weight to be at least ", groups,
" at dimension 0, but got weight of size ", weight_sizes, " instead");
TORCH_CHECK(weight_sizes[0] % groups == 0,
"Given groups=", groups, ", expected weight to be divisible by ",
groups, " at dimension 0, but got weight of size [", weight_sizes,
"] instead");
if (!transposed) {
std::vector<int64_t> input_shape;
std::vector<int64_t> kernel_shape;
bool kernel_size_correct = true;
TORCH_CHECK(input.size(1) == (weight_sizes[1] * groups),
"Given groups=", groups, ", weight of size ", weight_sizes,
", expected input", input.sizes(), " to have ",
(weight_sizes[1] * groups), " channels, but got ", input.size(1),
" channels instead");
TORCH_CHECK(!bias.defined() || (bias.ndimension() == 1 && bias.size(0) == weight_sizes[0]),
"Given weight of size ", weight_sizes,
", expected bias to be 1-dimensional with ", weight_sizes[0], " elements",
", but got bias of size ", bias.sizes(), " instead");
for (const auto i : c10::irange(2, k)) {
input_shape.push_back(input.size(i) + 2 * padding[i-2]);
// log new kernel size considering dilation
kernel_shape.push_back(dilation[i-2] * (weight_sizes[i]-1) + 1);
if (input_shape.back() < kernel_shape.back()) {
kernel_size_correct = false;
}
}
TORCH_CHECK(input_shape.size() == kernel_shape.size(), "Inconsistent shape between Input and Kernel");
if (!kernel_size_correct) {
// If kernel size is incorrect
std::ostringstream input_ss;
std::ostringstream kernel_ss;
std::ostringstream output_ss;
std::string separator = "";
for (int i = 0, len = input_shape.size(); i < len; ++i) {
input_ss << separator << input_shape[i];
kernel_ss << separator << kernel_shape[i];
separator = " x ";
}
AT_ERROR("Calculated padded input size per channel: (", input_ss.str(), "). "
"Kernel size: (", kernel_ss.str(), "). Kernel size can't be greater than actual input size");
}
} else { // transposed
TORCH_CHECK(input.size(1) == weight_sizes[0],
"Given transposed=", transposed, ", weight of size ", weight_sizes,
", expected input", input.sizes(), " to have ", weight_sizes[0],
" channels, but got ", input.size(1), " channels instead");
TORCH_CHECK(!bias.defined() || (bias.ndimension() == 1 && bias.size(0) == weight_sizes[1] * groups),
"Given transposed=", transposed, ", weight of size ", weight_sizes,
", expected bias to be 1-dimensional with ", weight_sizes[1] * groups, " elements",
", but got bias of size ", bias.sizes(), " instead");
}
}
static auto view4d(const at::Tensor& tensor) -> at::Tensor {
TORCH_CHECK(tensor.ndimension() == 3,
"expected 3D tensor, got tensor with ", tensor.ndimension(),
" dimensions instead");
return tensor.unsqueeze(2);
}
static auto view3d(const at::Tensor& tensor) -> at::Tensor {
TORCH_CHECK(tensor.ndimension() == 4,
"expected 4D tensor, got tensor with ", tensor.ndimension(),
" dimensions instead");
return tensor.squeeze(2);
}
static at::Tensor subtensor(at::Tensor& tensor, int dim, int groups, int g) {
if (!tensor.defined()) {
return at::Tensor();
}
int64_t n = tensor.sizes()[dim] / groups;
return tensor.narrow(dim, n * g, n).contiguous();
}
at::Tensor conv1d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation, int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
false, {0}, groups);
}
at::Tensor conv2d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation, int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
false, {{0, 0}}, groups);
}
at::Tensor conv3d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation, int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
false, {{0, 0, 0}}, groups);
}
static Tensor convolution_same(
const Tensor &input, const Tensor &weight, const Tensor &bias,
IntArrayRef stride, IntArrayRef dilation, int64_t groups) {
auto k = weight.dim();
auto dim = k - 2;
TORCH_CHECK(dim > 0, "weight should have at least three dimensions");
auto weight_sizes = weight.sizes();
auto input_sizes = input.sizes();
TORCH_CHECK(k == input.dim(),
"Expected ", k, "-dimensional input for ",
k, "-dimensional weight", weight_sizes, ", but got ",
input.dim(), "-dimensional input of size ",
input.sizes(), " instead");
TORCH_CHECK(stride.size() == dim || stride.size() == 1,
"stride cannot broadcast to ", dim, " dimensions");
TORCH_CHECK(dilation.size() == dim || dilation.size() == 1,
"dilation cannot broadcast to ", dim, " dimensions");
for (int64_t i = 0; i < stride.size(); ++i) {
TORCH_CHECK(stride[i] == 1, "padding='same' is not supported for strided convolutions");
}
// Calculate the correct padding
DimVector padding_l, padding_r;
bool symmetric_padding = true;
for (int64_t i = 0; i < dim; ++i) {
auto s = stride.size() == 1 ? stride[0] : stride[i];
auto d = dilation.size() == 1 ? dilation[0] : dilation[i];
auto pad = pooling_same_mode_padding_lr(
input_sizes[i + 2], weight_sizes[i + 2], s, d);
padding_l.push_back(pad.first);
padding_r.push_back(pad.second);
if (pad.first != pad.second) {
symmetric_padding = false;
}
}
if (symmetric_padding) {
// All backends handle symmetric padding natively
DimVector output_padding(static_cast<size_t>(dim));
return native::convolution(input, weight, bias, stride, padding_l, dilation,
false, output_padding, groups);
}
TORCH_WARN_ONCE("Using padding='same' with even kernel lengths and odd dilation may"
" require a zero-padded copy of the input be created");
SmallVector<int64_t, kDimVectorStaticSize * 2> pad_nd(static_cast<size_t>(2 * dim));
for (int i = 0; i < dim; ++i) {
// Apply padding by the difference, leaving only a symmetric padding
auto delta_pad = padding_r[i] - padding_l[i];
auto pad_idx = 2 * (dim - 1 - i); // F.pad goes from last dim to first
if (delta_pad > 0) {
pad_nd[pad_idx + 1] = delta_pad;
} else {
pad_nd[pad_idx] = delta_pad;
padding_l[i] = padding_r[i];
}
}
auto padded_input = at::constant_pad_nd(input, pad_nd, 0);
DimVector output_padding(static_cast<size_t>(dim));
return at::convolution(padded_input, weight, bias, stride, padding_l,
dilation, false, output_padding, groups);
}
Tensor _convolution_mode(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, std::string padding, IntArrayRef dilation,
int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
if (padding == "same") {
return at::native::convolution_same(
input, weight, bias, stride, dilation, groups);
} else if (padding == "valid") {
const int64_t padding_[] = {0};
return at::native::convolution(
input, weight, bias, stride, padding_, dilation, false, padding_, groups);
}
TORCH_CHECK(false, "Invalid padding string: '", padding, "'");
}
at::Tensor conv1d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias,
IntArrayRef stride, std::string padding, IntArrayRef dilation,
int64_t groups) {
return at::_convolution_mode(
input, weight, bias, stride, std::move(padding), dilation, groups);
}
at::Tensor conv2d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias,
IntArrayRef stride, std::string padding, IntArrayRef dilation,
int64_t groups) {
return at::_convolution_mode(
input, weight, bias, stride, std::move(padding), dilation, groups);
}
at::Tensor conv3d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias,
IntArrayRef stride, std::string padding, IntArrayRef dilation,
int64_t groups) {
return at::_convolution_mode(
input, weight, bias, stride, std::move(padding), dilation, groups);
}
at::Tensor conv_transpose1d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef output_padding, int64_t groups, IntArrayRef dilation) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
true, output_padding, groups);
}
at::Tensor conv_transpose2d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef output_padding, int64_t groups, IntArrayRef dilation) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
true, output_padding, groups);
}
at::Tensor conv_transpose3d(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef output_padding, int64_t groups, IntArrayRef dilation) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
return at::convolution(input, weight, bias, stride, padding, dilation,
true, output_padding, groups);
}
at::Tensor convolution(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation,
bool transposed, IntArrayRef output_padding, int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
auto& ctx = at::globalContext();
// See Note [Enabling Deterministic Operations]
bool deterministic = ctx.deterministicCuDNN() || ctx.deterministicAlgorithms();
return at::_convolution(input, weight, bias, stride, padding, dilation,
transposed, output_padding, groups,
ctx.benchmarkCuDNN(), deterministic, ctx.userEnabledCuDNN(), ctx.allowTF32CuDNN());
}
at::Tensor convolution_overrideable(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation,
bool transposed, IntArrayRef output_padding, int64_t groups) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
TORCH_CHECK_NOT_IMPLEMENTED(false, "convolution_overrideable not implemented. You are likely triggering this with tensor backend other than CPU/CUDA/MKLDNN, if this is intended, please use TORCH_LIBRARY_IMPL to override this function ");
}
at::Tensor _convolution(
const Tensor& input_r, const Tensor& weight_r, const c10::optional<Tensor>& bias_r_opt,
IntArrayRef stride_, IntArrayRef padding_, IntArrayRef dilation_,
bool transposed_, IntArrayRef output_padding_, int64_t groups_,
bool benchmark, bool deterministic, bool cudnn_enabled, bool allow_tf32) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias_r = c10::value_or_else(bias_r_opt, [] {return Tensor();});
const bool input_is_mkldnn = input_r.is_mkldnn();
auto input = input_r;
auto weight = weight_r;
auto bias = bias_r;
auto k = weight.ndimension();
c10::IntArrayRef weight_sizes = weight.sizes();
int64_t dim = k - 2;
TORCH_CHECK(dim > 0, "weight should have at least three dimensions");
ConvParams params;
params.stride = expand_param_if_needed(stride_, "stride", dim);
params.padding = expand_param_if_needed(padding_, "padding", dim);
params.dilation = expand_param_if_needed(dilation_, "dilation", dim);
params.transposed = transposed_;
params.output_padding = expand_param_if_needed(output_padding_, "output_padding", dim);
params.groups = groups_;
params.benchmark = benchmark;
params.deterministic = deterministic;
params.cudnn_enabled = cudnn_enabled;
params.allow_tf32 = allow_tf32;
check_shape_forward(input, weight_sizes, bias, params);
if (input.size(0) == 0) {
// don't send empty inputs through backends
// but need to compute correct output size first and set up history for params
std::vector<int64_t> o;
if (!params.transposed) {
o = conv_output_size(input.sizes(), weight_sizes, params.padding,
params.stride, params.dilation);
} else {
o = conv_input_size(input.sizes(), weight_sizes, params.padding,
params.output_padding, params.stride, params.dilation,
params.groups);
}
if (input_is_mkldnn && weight.is_mkldnn()) {
// mkldnn will error on the below 0-dim handling code
return empty_mkldnn(
o,
optTypeMetaToScalarType(input.options().dtype_opt()),
input.options().layout_opt(),
input.options().device_opt(),
input.options().pinned_memory_opt());
}
auto weight_view = at::_unsafe_view(weight, -1);
auto out = input*weight_view[0];
if (bias.defined())
out.add_(bias[0]);
return out.view(o);
}
if (k == 3) {
// avoid accidentally going through NHWC for permuted 3d input.
if (!input_is_mkldnn) {
input = input.contiguous();
}
params.view1d_as_2d();
input = view4d(input);
weight = view4d(weight);
}
at::MemoryFormat cudnn_memory_format = at::MemoryFormat::Contiguous;
if (cudnn_conv_use_channels_last(input, weight)) {
cudnn_memory_format = (k == 5) ? at::MemoryFormat::ChannelsLast3d : at::MemoryFormat::ChannelsLast;
}
Tensor output;
if (params.is_depthwise(input, weight)) {
/* output.resize_(output_size(input, weight)); */
auto kernel_size = weight.sizes().slice(2);
auto stride = params.stride;
auto padding = params.padding;
auto dilation = params.dilation;
if (params.use_cudnn_depthwise(input, weight)) {
output = at::cudnn_convolution(
input.contiguous(cudnn_memory_format), weight,
padding, stride, dilation, params.groups, params.benchmark, params.deterministic, params.allow_tf32);
if (bias.defined()) {
output.add_(reshape_bias(input.dim(), bias));
}
} else if (params.use_miopen(input, weight, bias.defined())){
output = at::miopen_depthwise_convolution(
input.contiguous(), weight, bias,
padding, stride, dilation, params.groups, params.benchmark, params.deterministic);
} else {
if (input.ndimension() == 4) {
output = at::thnn_conv_depthwise2d(input.contiguous(), weight, kernel_size, bias, stride, padding, dilation);
}
else {
TORCH_CHECK(input.ndimension() == 5);
output = at::conv_depthwise3d(input.contiguous(), weight, kernel_size, bias, stride, padding, dilation);
}
}
} else if (params.use_cudnn(input, weight)) {
TORCH_CHECK(input.options().type_equal(weight.options()),
"Input type (", input.toString(), ") and weight type (", weight.toString(),
") should be the same");
TORCH_CHECK(!bias.defined() || (input.options().type_equal(bias.options())),
"Input type (", input.toString(), ") and bias type (", bias.toString(),
") should be the same");
if (params.transposed) {
output = at::cudnn_convolution_transpose(
input.contiguous(cudnn_memory_format), weight,
params.padding, params.output_padding, params.stride, params.dilation, params.groups, params.benchmark, params.deterministic, params.allow_tf32);
if (bias.defined()) {
output.add_(reshape_bias(input.dim(), bias));
}
} else {
output = at::cudnn_convolution(
input.contiguous(cudnn_memory_format), weight,
params.padding, params.stride, params.dilation, params.groups, params.benchmark, params.deterministic, params.allow_tf32);
if (bias.defined()) {
output.add_(reshape_bias(input.dim(), bias));
}
}
} else if (params.use_miopen(input, weight, bias.defined())) {
TORCH_CHECK(input.options().type_equal(weight.options()),
"Input type (", input.toString(), ") and weight type (", weight.toString(),
") should be the same");
TORCH_CHECK(!bias.defined() || (input.options().type_equal(bias.options())),
"Input type (", input.toString(), ") and bias type (", bias.toString(),
") should be the same");
if (params.transposed) {
output = at::miopen_convolution_transpose(
input.contiguous(), weight, bias,
params.padding, params.output_padding, params.stride, params.dilation, params.groups, params.benchmark, params.deterministic);
} else {
output = at::miopen_convolution(
input.contiguous(), weight, bias,
params.padding, params.stride, params.dilation, params.groups, params.benchmark, params.deterministic);
}
} else if (params.use_mkldnn(input, weight)) {
#if AT_MKLDNN_ENABLED()
TORCH_CHECK(input.options().type_equal(weight.options())
|| (input.is_mkldnn() && weight.device().is_cpu() && weight.scalar_type() == kFloat),
"Input type (", input.toString(), ") and weight type (", weight.toString(),
") should be the same or input should be a MKLDNN tensor and weight is a dense tensor");
TORCH_CHECK(!bias.defined() || (input.options().type_equal(bias.options()))
|| (input.is_mkldnn() && bias.device().is_cpu() && bias.scalar_type() == kFloat),
"Input type (", input.toString(), ") and bias type (", bias.toString(),
") should be the same or input should be a MKLDNN tensor and bias is a dense tensor");
if (!input_is_mkldnn) {
output = at::mkldnn_convolution(input.contiguous(), weight.contiguous(), bias.defined() ? bias.contiguous() : bias,
params.padding, params.stride, params.dilation, params.groups);
} else {
// do not call contiguous on mkldnn tensor
output = at::mkldnn_convolution(input, weight, bias,
params.padding, params.stride, params.dilation, params.groups);
}
#endif
} else if (params.use_xnnpack(input, weight, bias)) {
// Using prepacked conv is preferred, but XNNPACK is still the fastest
// option for NHWC.
output = xnnpack::convolution2d(
input,
weight,
bias,
params.padding,
params.stride,
params.dilation,
params.groups);
} else if (params.use_cpu_depthwise3x3_winograd(input, weight, bias)) {
output = convolution_depthwise3x3_winograd_stub(
input.device().type(),
input,
weight,
bias,
params.stride,
params.padding,
params.groups);
} else if (
!params.transposed && (input.ndimension() == 5) &&
(input.device().is_cpu()) &&
!params.is_dilated()) {
// fast path for grouped conv3d
output = at::slow_conv3d(
input,
weight,
weight.sizes().slice(2),
bias,
params.stride,
params.padding);
} else if (input.device().is_cpu() || input.is_cuda()) {
if (params.groups == 1) {
output = at::_convolution_nogroup(
input.contiguous(), weight, bias, params.stride, params.padding, params.dilation, params.transposed, params.output_padding);
} else {
std::vector<Tensor> outputs(params.groups);
input = input.contiguous();
for (int g = 0; g < params.groups; ++g) {
auto input_g = subtensor(input, 1, params.groups, g);
auto weight_g = subtensor(weight, 0, params.groups, g);
auto bias_g = subtensor(bias, 0, params.groups, g);
outputs[g] = at::_convolution_nogroup(
input_g, weight_g, bias_g, params.stride, params.padding, params.dilation, params.transposed, params.output_padding);
}
output = at::cat(outputs, 1);
}
} else {
// Only reach here when input is backend with out-of-source implementation.
output = at::convolution_overrideable(input, weight, bias, params.stride, params.padding, params.dilation, params.transposed, params.output_padding, params.groups);
}
if (k == 3) {
output = view3d(output);
}
return output;
}
at::Tensor _convolution(
const Tensor& input_r, const Tensor& weight_r, const c10::optional<Tensor>& bias_r_opt,
IntArrayRef stride_, IntArrayRef padding_, IntArrayRef dilation_,
bool transposed_, IntArrayRef output_padding_, int64_t groups_,
bool benchmark, bool deterministic, bool cudnn_enabled)
{
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias_r = c10::value_or_else(bias_r_opt, [] {return Tensor();});
return at::_convolution(input_r, weight_r, bias_r, stride_, padding_, dilation_, transposed_, output_padding_, groups_, benchmark, deterministic, cudnn_enabled, at::globalContext().allowTF32CuDNN());
}
// A generic function for convolution implementations which don't
// natively implement groups (e.g., not CuDNN).
at::Tensor _convolution_nogroup(
const Tensor& input, const Tensor& weight, const c10::optional<Tensor>& bias_opt,
IntArrayRef stride, IntArrayRef padding, IntArrayRef dilation,
bool transposed, IntArrayRef output_padding) {
// See [Note: hacky wrapper removal for optional tensor]
const Tensor& bias = c10::value_or_else(bias_opt, [] {return Tensor();});
ConvParams params;
params.stride = stride.vec();
params.padding = padding.vec();
params.dilation = dilation.vec();
params.transposed = transposed;
params.output_padding = output_padding.vec();
params.groups = 1;
params.benchmark = false;
params.deterministic = false;
params.cudnn_enabled = false;