New Board Definition: iCE40HX8K-B-EVN

[fdx1601]

Hi, this is more a question than an issue I suppose ...

In the boards definition "boards/icestick.json" it states a value I wasn't able to trace back to the datasheet.

  "upload": {
    "maximum_ram_size": 32768,
    "maximum_size": 32768
  }

On page 2 of the "iCE40TM LP/HX Family Data Sheet" it says for the "HX1K":

RAM4K Memory Blocks: 16
RAM4K RAM bits: 64K

So, shouldn't be the "maximum_ram_size" and "maximum_size" of that size?

FYI I don't own the icestick board but am planning to get the "iCE40HX8K-B-EVN". For that reason I was trying to create a board file.

This is what I have so far:

{
  "build": {
    "core": "iCE40HX8KBreakoutBoard",
    "cpu": "fpga",
    "f_cpu": "12000000L",
    "hwids": [
      [
        "0x0403",
        "0x6010"
      ]
    ],
    "mcu": "iCE40-HX8K-CT256",
    "pack": "ct256",
    "size": "8k",
    "type": "hx"
  },
  "frameworks": [
    "icestorm"
  ],
  "name": "Lattice iCE40-HX8K Breakout Board",
  "upload": {
    "maximum_ram_size": 65536,
    "maximum_size": 65536
  },
  "url": "http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard",
  "vendor": "Lattice"
}

I tried the building process with a simple LED example and all stages are beeing processed:

[Wed Apr 18 13:25:01 2018] Processing ice40 (platform: lattice_ice40; board: iCE40HX8KBreakoutBoard; framework: icestorm)
--------------------------------------------------------------------------------
Verbose mode can be enabled via `-v, --verbose` option
yosys -p "synth_ice40 -blif .pioenvs/ice40/hardware.blif" -q src/main.v
Warning: Wire top.counter has an unprocessed 'init' attribute.
arachne-pnr -d 8k -P ct256 -p /Users/ts/Documents/PlatformIO/Projects/Hello_FPGA/src/main.pcf -o .pioenvs/ice
40/hardware.asc .pioenvs/ice40/hardware.blif
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
supported packages: cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif .pioenvs/ice40/hardware.blif...
prune...
read_pcf /Users/ts/Documents/PlatformIO/Projects/Hello_FPGA/src/main.pcf...
instantiate_io...
pack...

After packing:
IOs          9 / 206
GBs          0 / 8
GB_IOs     0 / 8
LCs          28 / 7680
DFF        3
CARRY      2
CARRY, DFF 23
DFF PASS   0
CARRY PASS 1
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         0 / 2

place_constraints...
promote_globals...
promoted hwclk$2, 26 / 26
promoted 1 nets
1 clk
1 globals
1 clk
realize_constants...
realized 1
place...
initial wire length = 496
at iteration #50: temp = 21.5721, wire length = 116
at iteration #100: temp = 9.44191, wire length = 110
at iteration #150: temp = 2.0266, wire length = 78
at iteration #200: temp = 0.00158118, wire length = 51
final wire length = 51

After placement:
PIOs       9 / 206
PLBs       6 / 960
BRAMs      0 / 32
 
place time 0.04s
route...
pass 1, 0 shared.
 
After routing:
span_4     19 / 29696
span_12    2 / 5632
 
route time 0.09s
write_txt .pioenvs/ice40/hardware.asc...
icepack .pioenvs/ice40/hardware.asc .pioenvs/ice40/hardware.bin
========================= [SUCCESS] Took 14.95 seconds =========================