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i2sclock.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 23:10:58 October 03, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# i2sclock_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY i2sclock
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:10:58 OCTOBER 03, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/naoki/altera/i2s_rj16_divivor/simulation/qsim/ -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_15 -to mclk
set_location_assignment PIN_7 -to bck
set_location_assignment PIN_1 -to sclk
set_location_assignment PIN_3 -to sda
set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to sda
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH test_i2sclock -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_i2sclock -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_i2sclock
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_i2sclock -section_id test_i2sclock
set_global_assignment -name EDA_TEST_BENCH_FILE test_i2sclock.v -section_id test_i2sclock
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to sclk
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to sda
set_global_assignment -name VERILOG_FILE internal_osc.v
set_global_assignment -name VERILOG_FILE i2sclock.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name VERILOG_FILE I2C_to_GPIO.v
set_global_assignment -name VERILOG_FILE test_i2sclock.v
set_global_assignment -name QIP_FILE internal_osc.qip
set_location_assignment PIN_19 -to mclk_in
set_location_assignment PIN_5 -to lrck
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to mclk_in
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to bck
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bck
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to lrck
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to mclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to bck
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to lrck
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mclk_in