From 5fbe3a8aec4b4d5d4cfbd9b5739fe864799c7765 Mon Sep 17 00:00:00 2001 From: SiHuaN Date: Tue, 2 Sep 2025 13:00:21 +0800 Subject: [PATCH] fix bitrev C intrinsic test error --- clang/lib/CodeGen/CGBuiltin.cpp | 4 ++-- clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 2a19e1ddc3fd..304e20802913 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -19232,7 +19232,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__rv_add16: case RISCV::BI__rv_add32: case RISCV::BI__rv_ave: - case RISCV::BI__rv_bitrev: case RISCV::BI__rv_bpick: case RISCV::BI__rv_clrs8: case RISCV::BI__rv_clrs16: @@ -19374,7 +19373,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, BUILTIN_ID(add16) BUILTIN_ID(add32) BUILTIN_ID(ave) - BUILTIN_ID(bitrev) BUILTIN_ID(bpick) BUILTIN_ID(clrs8) BUILTIN_ID(clrs16) @@ -19598,6 +19596,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, } // Intrinsic type is obtained from ResultType and Ops[1]. + case RISCV::BI__rv_bitrev: case RISCV::BI__rv_kdmabb: case RISCV::BI__rv_kdmabt: case RISCV::BI__rv_kdmatt: @@ -19652,6 +19651,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); + BUILTIN_ID(bitrev) BUILTIN_ID(kdmabb) BUILTIN_ID(kdmabt) BUILTIN_ID(kdmatt) diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c b/clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c index 4f6d39117cd9..228598f607c1 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics/rv32p.c @@ -37,7 +37,7 @@ long ave(long a, long b) { // CHECK-RV32-LABEL: @bitrev( // CHECK-RV32-NEXT: entry: -// CHECK-RV32-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.riscv.bitrev.i32(i32 [[A:%.*]], i32 [[B:%.*]]) +// CHECK-RV32-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.riscv.bitrev.i32.i32(i32 [[A:%.*]], i32 [[B:%.*]]) // CHECK-RV32-NEXT: ret i32 [[TMP0]] // unsigned long bitrev(unsigned long a, unsigned long b) {