修复AHCI错误的MMIO地址获取问题

Author: xiaoyi1212

src/core/main.c

@@ -27,6 +27,8 @@
 #include "shell.h"
 #include "iic/iic_core.h"
 #include "smbios.h"
+#include "rtl8169.h"
+#include "pcnet.h"
 
 // 编译器判断
 #if defined(__clang__)
@@ -103,15 +105,17 @@ void kmain(void) {
     ahci_setup();
     //xhci_setup();
 
-
+    //rtl8169_setup();
+    //pcnet_setup();
     pivfs_setup();
     init_pcb();
     smp_setup();
     build_stream_device();
-
     init_iic();
 
-    /*TODO*/ create_kernel_thread(terminal_flush_service, NULL, "TerminalFlush");
+
+
+    create_kernel_thread(terminal_flush_service, NULL, "TerminalFlush");
     create_kernel_thread((void *) shell_setup, NULL, "KernelShell");
     kinfo("Kernel load Done!");
     //beep();

src/driver/pci/ahci.c

@@ -6,19 +6,25 @@
 #include "alloc.h"
 #include "pcie.h"
 #include "io.h"
+#include "klog.h"
 
 static uint32_t ahci_ports[32];
 static uint32_t port_total = 0;
 static uint64_t ahci_ports_base_addr;
 HBA_MEM *hba_mem;
 
 static int check_type(HBA_PORT *port) {
-    uint32_t ssts = port->ssts;
+    port->cmd &= ~HBA_PxCMD_ST;
+    port->cmd &= ~HBA_PxCMD_FRE;
+    while (port->cmd & HBA_PxCMD_CR);
+    port->cmd |= HBA_PxCMD_FRE | HBA_PxCMD_ST;
 
+    uint32_t ssts = port->ssts;
     uint8_t ipm = (ssts >> 8) & 0x0F;
     uint8_t det = ssts & 0x0F;
-    if (det != HBA_PORT_DET_PRESENT) return AHCI_DEV_NULL;
-    if (ipm != HBA_PORT_IPM_ACTIVE) return AHCI_DEV_NULL;
+    if (det != HBA_PORT_DET_PRESENT || ipm != HBA_PORT_IPM_ACTIVE) return AHCI_DEV_NULL;
+
+    logkf("SATA drive found at port %d\n", port_total);
 
     switch (port->sig) {
         case SATA_SIG_ATAPI:
@@ -78,17 +84,17 @@ void ahci_port_rebase(HBA_PORT *port, int portno) {
     // Command list maxim size = 32*32 = 1K per port
     port->clb = ahci_ports_base_addr + (portno << 10);
     port->clbu = 0;
-    memset((void *) (port->clb), 0, 1024);
+    memset((void *) phys_to_virt(port->clb), 0, 1024);
 
     // FIS offset: 32K+256*portno
     // FIS entry size = 256 bytes per port
     port->fb = ahci_ports_base_addr + (32 << 10) + (portno << 8);
     port->fbu = 0;
-    memset((void *) (port->fb), 0, 256);
+    memset((void *) phys_to_virt(port->fb), 0, 256);
 
     // Command table offset: 40K + 8K*portno
     // Command table size = 256*32 = 8K per port
-    HBA_CMD_HEADER *cmdheader = (HBA_CMD_HEADER *) (port->clb);
+    HBA_CMD_HEADER *cmdheader = (HBA_CMD_HEADER *) phys_to_virt(port->clb);
     for (int i = 0; i < 32; i++) {
         cmdheader[i].prdtl = 8; // 8 prdt entries per command table
         // 256 bytes per command table, 64+16+48+16*8
@@ -107,23 +113,24 @@ bool ahci_identify(HBA_PORT *port, void *buf) {
     int slot = find_cmdslot(port);
     if (slot == -1) return false;
 
-    HBA_CMD_HEADER *cmdheader = (HBA_CMD_HEADER *) port->clb;
+    HBA_CMD_HEADER *cmdheader = (HBA_CMD_HEADER *) phys_to_virt(port->clb);
+    printk("cmdheader: %p\n",cmdheader);
     cmdheader += slot;
     cmdheader->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t); // Command FIS size
     cmdheader->w = 0;                                 // Read from device
     cmdheader->prdtl = 1;                                 // PRDT entries count
     cmdheader->c = 1;
     HBA_CMD_TBL *cmdtbl = (HBA_CMD_TBL *) (cmdheader->ctba);
     memset(cmdtbl, 0, sizeof(HBA_CMD_TBL) + (cmdheader->prdtl - 1) * sizeof(HBA_PRDT_ENTRY));
-
+    printk("MEMSET cmdtbl: %p\n",cmdtbl);
     cmdtbl->prdt_entry[0].dba = (uint64_t) buf;
     cmdtbl->prdt_entry[0].dbau = 0;
     cmdtbl->prdt_entry[0].dbc = 0x200 - 1;
     cmdtbl->prdt_entry[0].i = 1;
 
     // Setup command
     FIS_REG_H2D *cmdfis = (FIS_REG_H2D *) (&cmdtbl->cfis);
-
+    printk("cmdfis: %p\n",cmdfis);
     cmdfis->fis_type = FIS_TYPE_REG_H2D;
     cmdfis->c = 1;    // Command
     cmdfis->command = 0xec; // ATA IDENTIFY
@@ -140,6 +147,7 @@ bool ahci_identify(HBA_PORT *port, void *buf) {
 
     port->ci = 1 << slot; // Issue command
 
+    printk("III slot: %d\n",slot);
     // Wait for completion
     while (1) {
         // In some longer duration reads, it may be helpful to spin on the DPS bit
@@ -152,6 +160,8 @@ bool ahci_identify(HBA_PORT *port, void *buf) {
         }
     }
 
+    printk("I\n");
+
     // Check again
     if (port->is & HBA_PxIS_TFES) {
         kwarn("Read ahci disk error\n");
@@ -171,14 +181,17 @@ void ahci_search_ports(HBA_MEM *abar) {
             int dt = check_type(&abar->ports[i]);
             if (dt == AHCI_DEV_SATA) {
                 ahci_ports[port_total++] = i;
+                logkf("SATA drive found at port %d\n", i);
             } else if (dt == AHCI_DEV_SATAPI) {
                 ahci_ports[port_total++] = i;
+                logkf("SATAPI drive found at port %d\n", i);
             } else if (dt == AHCI_DEV_SEMB) {
+                logkf("SEMB drive found at port %d\n", i);
             } else if (dt == AHCI_DEV_PM) {
+                logkf("PM drive found at port %d\n", i);
             } else {
             }
         }
-
         pi >>= 1;
         i++;
     }
@@ -212,10 +225,12 @@ void ahci_setup() {
         hba_mem = (HBA_MEM*)device->bars[5].address;
     }
 
-    hba_mem->ghc |= AHCI_GHC_AE;
+    hba_mem->ghc |= (1 << 31);
 
     ahci_ports_base_addr = (uint64_t) malloc(1048576);
 
+    logkf("AHCI cap %x, vs %x\n", hba_mem->cap,hba_mem->vs);
+
     ahci_search_ports(hba_mem);
     uint32_t i;
     for (i = 0; i < port_total; i++) {

src/driver/pci/nvme.c

@@ -164,7 +164,7 @@ void nvme_setup() {
         capability = (nvme_capability *) phys_to_virt(device->bars[0].address);
     }
 
-    page_map_range_to(get_kernel_pagedir(), device->bars[0].address, 0x1000, KERNEL_PTE_FLAGS);
+    page_map_range_to(get_kernel_pagedir(), device->bars[0].address, 0x1000 * 2, KERNEL_PTE_FLAGS);
 
     if (!((capability->CAP >> 37) & 1)) {
         kerror("Nvme controller does not support nvme command set.\n");

src/driver/pci/pci.c

@@ -298,6 +298,11 @@ bool pci_bar_present(pci_device_t device,uint8_t bar){
     return read_pci(device,reg_index) != 0;
 }
 
+uint8_t pci_get_drive_irq(uint8_t bus, uint8_t slot, uint8_t func) {
+    return (uint8_t)
+            read_pci0(bus, slot, func, 0x3c);
+}
+
 static void load_pci_device(uint32_t BUS, uint32_t Equipment, uint32_t F){
     uint32_t value_c = read_pci0(BUS, Equipment, F, PCI_CONF_REVISION);
     uint32_t class_code = value_c >> 8;

src/driver/pci/pcnet.c

@@ -0,0 +1,28 @@
+#include "pcnet.h"
+#include "pcie.h"
+#include "pci.h"
+#include "kprint.h"
+#include "isr.h"
+#include "acpi.h"
+#include "io.h"
+
+void pcnet_setup(){
+    pcie_device_t *device = pcie_find_class(0x10220000);
+    if(device == NULL) {
+        pci_device_t pci_device = pci_find_class(0x10220000);
+        if (pci_device == NULL) return;
+        uint32_t conf = pci_read_command_status(pci_device);
+        conf |= PCI_COMMAND_MEMORY;
+        conf |= PCI_RCMD_BUS_MASTER;
+        conf |= PCI_COMMAND_IO;
+        pci_write_command_status(pci_device, conf);
+        base_address_register reg = find_bar(pci_device, 0);
+        if (reg.address == NULL) {
+            kerror("Pcnet pci bar 0 is null.");
+            return;
+        }
+        ioapic_add(pcnet, pci_get_drive_irq(pci_device->bus, pci_device->slot, pci_device->func));
+    } else {
+        ioapic_add(pcnet, pci_get_drive_irq(device->bus, device->slot, device->func));
+    }
+}

src/driver/pci/rtl8169.c

@@ -0,0 +1,61 @@
+#include "rtl8169.h"
+#include "pci.h"
+#include "pcie.h"
+#include "hhdm.h"
+#include "io.h"
+#include "kprint.h"
+
+RTL8169_Regs *rtl8169;
+RTL8169_Desc tx_desc[TX_DESC_COUNT] __attribute__((aligned(256)));
+RTL8169_Desc rx_desc[RX_DESC_COUNT] __attribute__((aligned(256)));
+
+void rtl8169_reset() {
+    rtl8169->Command = 0x10;
+    while (rtl8169->Command & 0x10) __asm__ volatile("pause");
+}
+
+void rtl8169_setup_descriptors() {
+    rtl8169->TxDesc = (uint32_t) virt_to_phys((uint64_t)&tx_desc);  // 设置 TX 描述符基地址
+    rtl8169->RxDesc = (uint32_t)&rx_desc;  // 设置 RX 描述符基地址
+}
+
+void rtl8169_setup(){
+    pcie_device_t *device = pcie_find_class(0x020000);
+    if(device == NULL){
+        pci_device_t pci_device = pci_find_class(0x020000);
+        if(pci_device == NULL) return;
+        uint32_t conf = pci_read_command_status(pci_device);
+        conf |= PCI_COMMAND_MEMORY;
+        conf |= PCI_RCMD_BUS_MASTER;
+        conf |= PCI_COMMAND_IO;
+        pci_write_command_status(pci_device, conf);
+        base_address_register reg = find_bar(pci_device,0);
+        if(reg.address == NULL){
+            kerror("Rtl8169 pci bar 0 is null.");
+            return;
+        }
+        rtl8169 = (RTL8169_Regs *) phys_to_virt((uint64_t)reg.address);
+    }else{
+        uint32_t conf = pcie_read_command(device, 0x04);
+        conf |= PCI_RCMD_BUS_MASTER;
+        conf |= PCI_COMMAND_MEMORY;
+        conf |= PCI_COMMAND_IO;
+        pcie_write_command(device, 0x04, conf);
+        rtl8169 = (RTL8169_Regs *)device->bars[0].address;
+        if(rtl8169 == NULL){
+            kerror("Rtl8169 pci bar 0 is null.");
+            return;
+        }
+        rtl8169 = phys_to_virt((uint64_t)rtl8169);
+    }
+
+    rtl8169->Command = 0x0C;
+    rtl8169_setup_descriptors();
+
+    kinfo("Rtl8169 mac: %x:%x:%x:%x:%x:%x",rtl8169->MAC[0] & 0xFF,
+          (rtl8169->MAC[0] >> 8) & 0xFF,
+          (rtl8169->MAC[0] >> 16) & 0xFF,
+          (rtl8169->MAC[0] >> 24) & 0xFF,
+          rtl8169->MAC[1] & 0xFF,
+          (rtl8169->MAC[1] >> 8) & 0xFF);
+}

src/include/ahci.h

@@ -68,9 +68,9 @@ typedef struct tagHBA_CMD_HEADER {
 } __attribute__((packed)) HBA_CMD_HEADER;
 
 typedef volatile struct tagHBA_PORT {
-    uint64_t clb;       // 0x00, command list base address, 1K-byte aligned
-    uint64_t clbu;      // 0x04, command list base address upper 32 bits
-    uint64_t fb;        // 0x08, FIS base address, 256-byte aligned
+    uint32_t clb;       // 0x00, command list base address, 1K-byte aligned
+    uint32_t clbu;      // 0x04, command list base address upper 32 bits
+    uint32_t fb;        // 0x08, FIS base address, 256-byte aligned
     uint32_t fbu;       // 0x0C, FIS base address upper 32 bits
     uint32_t is;        // 0x10, interrupt status
     uint32_t ie;        // 0x14, interrupt enable

src/include/isr.h

@@ -1,7 +1,5 @@
 #pragma once
 
-
-
 #include "ctype.h"
 
 enum InterruptIndex {
@@ -10,7 +8,8 @@ enum InterruptIndex {
     mouse,
     hpet_timer,
     ide_primary,
-    ide_secondary
+    ide_secondary,
+    pcnet,
 };
 
 struct interrupt_frame {

src/include/pci.h

@@ -59,4 +59,5 @@ uint32_t get_pci_num();
 bool pci_bar_present(pci_device_t device,uint8_t bar);
 int pci_find_capability(pci_device_t device, uint8_t cap_id);
 void pci_set_msi(pci_device_t device,uint8_t vector);
+uint8_t pci_get_drive_irq(uint8_t bus, uint8_t slot, uint8_t func);
 void pci_setup();

src/include/pcnet.h

@@ -0,0 +1,3 @@
+#pragma once
+
+void pcnet_setup();