新增网络设备的独立注册机制, 扩展部分内核模块接口

Author: xiaoyi1212

module/all_include/driver_subsystem.h

@@ -2,25 +2,28 @@
 
 #include "cp_kernel.h"
 
+typedef errno_t (*netdev_send_t)(void *dev, void *data, uint32_t len);
+typedef errno_t (*netdev_recv_t)(void *dev, void *data, uint32_t len);
+
 typedef enum {
     VDISK_BLOCK,
     VDISK_STREAM,
-} vdisk_flag_t;
+} device_flag_t;
 
-typedef struct vdisk_device {
+typedef struct _device {
     size_t (*read_vbuf)(int drive, struct vecbuf *buffer, size_t number, size_t lba);
     size_t (*write_vbuf)(int drive, struct vecbuf *buffer, size_t number, size_t lba);
     size_t (*read)(int drive, uint8_t *buffer, size_t number, size_t lba);
     size_t (*write)(int drive, uint8_t *buffer, size_t number, size_t lba);
-    int (*ioctl)(struct vdisk_device *device, size_t req, void *handle);
+    int (*ioctl)(struct _device *device, size_t req, void *handle);
     int (*poll)(size_t events);
     void *(*map)(int drive, void *addr, uint64_t len);
-    int          flag;
-    size_t       size;        // 大小
-    size_t       sector_size; // 扇区大小
-    vdisk_flag_t type;
-    char         drive_name[50];
-} vdisk; // 块设备
+    int           flag;
+    size_t        size;        // 大小
+    size_t        sector_size; // 扇区大小
+    device_flag_t type;
+    char          drive_name[50];
+} device_t; // 块设备
 
 typedef struct {
     uint64_t address;
@@ -53,10 +56,22 @@ typedef struct {
     pci_device_op_t *op;
 } pci_device_t;
 
-int    regist_vdisk(vdisk vd);
+typedef struct netdev {
+    uint8_t       mac[6];
+    uint32_t      mtu;
+    void         *desc;
+    netdev_send_t send;
+    netdev_recv_t recv;
+} netdev_t;
+
+void regist_netdev(void *desc, uint8_t *mac, uint32_t mtu, netdev_send_t send, netdev_recv_t recv);
+errno_t netdev_send(netdev_t *dev, void *data, uint32_t len);
+errno_t netdev_recv(netdev_t *dev, void *data, uint32_t len);
+
+int    regist_device(device_t vd);
 void  *driver_phys_to_virt(uint64_t phys_addr);
-size_t vdisk_read(size_t lba, size_t number, void *buffer, int drive);
-size_t vdisk_write(size_t lba, size_t number, const void *buffer, int drive);
+size_t device_read(size_t lba, size_t number, void *buffer, int drive);
+size_t device_write(size_t lba, size_t number, const void *buffer, int drive);
 
 pci_device_t *pci_find_vid_did(uint16_t vendor_id, uint16_t device_id);
 pci_device_t *pci_find_class(uint32_t class_code);

module/all_include/mem_subsystem.h

@@ -51,6 +51,7 @@ void    *virt_to_phys(uint64_t virt_addr);
 uint64_t page_virt_to_phys(uint64_t va);
 void    *driver_phys_to_virt(uint64_t phys_addr);
 void    *driver_virt_to_phys(uint64_t virt_addr);
+void     unmap_page_range(page_directory_t *directory, uint64_t vaddr, uint64_t size);
 
 uint64_t get_reserved_memory();
 uint64_t get_all_memory();

module/e1000/e1000.c

@@ -201,13 +201,109 @@ int e1000_init(void *mmio_base) {
     // Disable interrupts (polling mode)
     e1000_write32(dev, E1000_IMC, 0xFFFFFFFF);
 
-    // Store device and register with network framework
     e1000_devices[e1000_device_count++] = dev;
-    // regist_netdev(dev, dev->mac, dev->mtu, e1000_send, e1000_receive);
+    regist_netdev(dev, dev->mac, dev->mtu, e1000_send, e1000_receive);
 
     return 0;
 }
 
+bool e1000_has_packets(e1000_device_t *dev) {
+    uint16_t next_rx = (dev->rx_tail + 1) % E1000_NUM_RX_DESC;
+    return (dev->rx_descs[next_rx].status & E1000_RXD_STAT_DD) != 0;
+}
+
+errno_t e1000_send(void *dev_desc, void *data, uint32_t len) {
+    e1000_device_t *dev = (e1000_device_t *)dev_desc;
+
+    if (len > E1000_MTU || len == 0) { return -1; }
+
+    // Check if we have a free TX descriptor
+    uint16_t next_tail = (dev->tx_tail + 1) % E1000_NUM_TX_DESC;
+    if (next_tail == dev->tx_head) {
+        // TX queue full
+        return -1;
+    }
+
+    // Allocate buffer for packet
+    uint64_t phy_      = alloc_frames(len / PAGE_SIZE + 1);
+    void    *tx_buffer = driver_phys_to_virt(phy_);
+    page_map_range(get_current_directory(), (uint64_t)tx_buffer, phy_, len, KERNEL_PTE_FLAGS);
+    if (!tx_buffer) { return -1; }
+
+    // Copy data to buffer
+    memcpy(tx_buffer, data, len);
+
+    // Setup TX descriptor
+    dev->tx_descs[dev->tx_tail].buffer_addr = (uint64_t)virt_to_phys(phy_);
+    dev->tx_descs[dev->tx_tail].length      = len;
+    dev->tx_descs[dev->tx_tail].cmd    = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
+    dev->tx_descs[dev->tx_tail].status = 0;
+
+    // Store buffer pointer for later cleanup
+    dev->tx_buffers[dev->tx_tail] = tx_buffer;
+
+    // Update tail pointer
+    dev->tx_tail = next_tail;
+    e1000_write32(dev, E1000_TDT, dev->tx_tail);
+
+    // Poll for completion
+    while (!(dev->tx_descs[dev->tx_head].status & E1000_TXD_STAT_DD)) {
+        // Wait for transmission to complete
+    }
+
+    // Clean up completed descriptors
+    while (dev->tx_head != dev->tx_tail) {
+        if (dev->tx_descs[dev->tx_head].status & E1000_TXD_STAT_DD) {
+            if (dev->tx_buffers[dev->tx_head]) {
+                unmap_page_range(get_current_directory(), (uint64_t)dev->tx_buffers[dev->tx_head],
+                                 len);
+                dev->tx_buffers[dev->tx_head] = NULL;
+            }
+            dev->tx_descs[dev->tx_head].status = 0;
+            dev->tx_head                       = (dev->tx_head + 1) % E1000_NUM_TX_DESC;
+        } else {
+            break;
+        }
+    }
+
+    return len;
+}
+
+// Receive packet (polling mode)
+errno_t e1000_receive(void *dev_desc, void *buffer, uint32_t buffer_size) {
+    e1000_device_t *dev = (e1000_device_t *)dev_desc;
+
+    uint16_t              next_rx = (dev->rx_tail + 1) % E1000_NUM_RX_DESC;
+    struct e1000_rx_desc *desc    = &dev->rx_descs[next_rx];
+
+    bool have_data = !!(desc->status & E1000_RXD_STAT_DD);
+
+    if (!have_data) {
+        // No packet available
+        return 0;
+    }
+
+    if (desc->errors & (E1000_RXD_ERR_CE | E1000_RXD_ERR_SE | E1000_RXD_ERR_SEQ |
+                        E1000_RXD_ERR_CXE | E1000_RXD_ERR_RXE)) {
+        // Packet has errors, discard it
+        goto cleanup;
+    }
+
+    uint32_t packet_len = desc->length;
+    if (packet_len > buffer_size) { packet_len = buffer_size; }
+
+    // Copy packet data to user buffer
+    memcpy(buffer, driver_phys_to_virt(desc->buffer_addr), packet_len);
+
+cleanup:
+    // Recycle the descriptor
+    desc->status = 0;
+    dev->rx_tail = next_rx;
+    e1000_write32(dev, E1000_RDT, dev->rx_tail);
+
+    return have_data ? packet_len : 0;
+}
+
 __attribute__((used)) __attribute__((visibility("default"))) int dlmain(void) {
     pci_device_t *device = pci_find_vid_did(0x8086, 0x100e);
     if (device == NULL) {

module/e1000/e1000.h

@@ -2,88 +2,88 @@
 
 // E1000 Device IDs
 #define E1000_DEVICE_ID_82540EM 0x100E
-#define MAX_E1000_DEVICES 8
+#define MAX_E1000_DEVICES       8
 
 // E1000 Register Definitions
-#define E1000_CTRL 0x0000     // Device Control
-#define E1000_STATUS 0x0008   // Device Status
-#define E1000_EERD 0x0014     // EEPROM Read
+#define E1000_CTRL     0x0000 // Device Control
+#define E1000_STATUS   0x0008 // Device Status
+#define E1000_EERD     0x0014 // EEPROM Read
 #define E1000_CTRL_EXT 0x0018 // Extended Device Control
-#define E1000_ICR 0x00C0      // Interrupt Cause Read
-#define E1000_IMS 0x00D0      // Interrupt Mask Set
-#define E1000_IMC 0x00D8      // Interrupt Mask Clear
-#define E1000_RCTL 0x0100     // RX Control
-#define E1000_TCTL 0x0400     // TX Control
-#define E1000_TIPG 0x0410     // TX Inter-packet Gap
-#define E1000_RDBAL 0x2800    // RX Descriptor Base Address Low
-#define E1000_RDBAH 0x2804    // RX Descriptor Base Address High
-#define E1000_RDLEN 0x2808    // RX Descriptor Length
-#define E1000_RDH 0x2810      // RX Descriptor Head
-#define E1000_RDT 0x2818      // RX Descriptor Tail
-#define E1000_RDTR 0x2820     // RX Delay Timer
-#define E1000_TDBAL 0x3800    // TX Descriptor Base Address Low
-#define E1000_TDBAH 0x3804    // TX Descriptor Base Address High
-#define E1000_TDLEN 0x3808    // TX Descriptor Length
-#define E1000_TDH 0x3810      // TX Descriptor Head
-#define E1000_TDT 0x3818      // TX Descriptor Tail
-#define E1000_TIDV 0x3820     // TX Interrupt Delay Value
-#define E1000_RA 0x5400       // Receive Address (MAC)
+#define E1000_ICR      0x00C0 // Interrupt Cause Read
+#define E1000_IMS      0x00D0 // Interrupt Mask Set
+#define E1000_IMC      0x00D8 // Interrupt Mask Clear
+#define E1000_RCTL     0x0100 // RX Control
+#define E1000_TCTL     0x0400 // TX Control
+#define E1000_TIPG     0x0410 // TX Inter-packet Gap
+#define E1000_RDBAL    0x2800 // RX Descriptor Base Address Low
+#define E1000_RDBAH    0x2804 // RX Descriptor Base Address High
+#define E1000_RDLEN    0x2808 // RX Descriptor Length
+#define E1000_RDH      0x2810 // RX Descriptor Head
+#define E1000_RDT      0x2818 // RX Descriptor Tail
+#define E1000_RDTR     0x2820 // RX Delay Timer
+#define E1000_TDBAL    0x3800 // TX Descriptor Base Address Low
+#define E1000_TDBAH    0x3804 // TX Descriptor Base Address High
+#define E1000_TDLEN    0x3808 // TX Descriptor Length
+#define E1000_TDH      0x3810 // TX Descriptor Head
+#define E1000_TDT      0x3818 // TX Descriptor Tail
+#define E1000_TIDV     0x3820 // TX Interrupt Delay Value
+#define E1000_RA       0x5400 // Receive Address (MAC)
 
 // Control Register Bits
-#define E1000_CTRL_RST (1 << 26)     // Reset
-#define E1000_CTRL_ASDE (1 << 5)     // Auto-Speed Detection Enable
-#define E1000_CTRL_SLU (1 << 6)      // Set Link Up
-#define E1000_CTRL_FRCSPD (1 << 11)  // Force Speed
+#define E1000_CTRL_RST     (1 << 26) // Reset
+#define E1000_CTRL_ASDE    (1 << 5)  // Auto-Speed Detection Enable
+#define E1000_CTRL_SLU     (1 << 6)  // Set Link Up
+#define E1000_CTRL_FRCSPD  (1 << 11) // Force Speed
 #define E1000_CTRL_FRCDPLX (1 << 12) // Force Duplex
 
 // RCTL Register Bits
-#define E1000_RCTL_EN (1 << 1)         // Enable
-#define E1000_RCTL_SBP (1 << 2)        // Store Bad Packets
-#define E1000_RCTL_UPE (1 << 3)        // Unicast Promiscuous Enable
-#define E1000_RCTL_MPE (1 << 4)        // Multicast Promiscuous Enable
-#define E1000_RCTL_LPE (1 << 5)        // Long Packet Enable
-#define E1000_RCTL_LBM_NONE (0 << 6)   // No Loopback
-#define E1000_RCTL_RDMTS_HALF (0 << 8) // RX Desc Min Threshold Size
-#define E1000_RCTL_MO_36 (36 << 12)    // Multicast Offset
-#define E1000_RCTL_BAM (1 << 15)       // Broadcast Accept Mode
-#define E1000_RCTL_SECRC (1 << 26)     // Strip Ethernet CRC
+#define E1000_RCTL_EN         (1 << 1)   // Enable
+#define E1000_RCTL_SBP        (1 << 2)   // Store Bad Packets
+#define E1000_RCTL_UPE        (1 << 3)   // Unicast Promiscuous Enable
+#define E1000_RCTL_MPE        (1 << 4)   // Multicast Promiscuous Enable
+#define E1000_RCTL_LPE        (1 << 5)   // Long Packet Enable
+#define E1000_RCTL_LBM_NONE   (0 << 6)   // No Loopback
+#define E1000_RCTL_RDMTS_HALF (0 << 8)   // RX Desc Min Threshold Size
+#define E1000_RCTL_MO_36      (36 << 12) // Multicast Offset
+#define E1000_RCTL_BAM        (1 << 15)  // Broadcast Accept Mode
+#define E1000_RCTL_SECRC      (1 << 26)  // Strip Ethernet CRC
 
 // TCTL Register Bits
-#define E1000_TCTL_EN (1 << 1)      // Enable
-#define E1000_TCTL_PSP (1 << 3)     // Pad Short Packets
-#define E1000_TCTL_CT_SHIFT 4       // Collision Threshold
-#define E1000_TCTL_COLD_SHIFT 12    // Collision Distance
-#define E1000_TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
+#define E1000_TCTL_EN         (1 << 1)  // Enable
+#define E1000_TCTL_PSP        (1 << 3)  // Pad Short Packets
+#define E1000_TCTL_CT_SHIFT   4         // Collision Threshold
+#define E1000_TCTL_COLD_SHIFT 12        // Collision Distance
+#define E1000_TCTL_SWXOFF     (1 << 22) // Software XOFF Transmission
 
 // EERD Register Bits
-#define E1000_EERD_START (1 << 0) // Start Read
-#define E1000_EERD_DONE (1 << 1)  // Read Done
-#define E1000_EERD_ADDR_SHIFT 2   // Address Shift
-#define E1000_EERD_DATA_SHIFT 16  // Data Shift
+#define E1000_EERD_START      (1 << 0) // Start Read
+#define E1000_EERD_DONE       (1 << 1) // Read Done
+#define E1000_EERD_ADDR_SHIFT 2        // Address Shift
+#define E1000_EERD_DATA_SHIFT 16       // Data Shift
 
 // RX Descriptor Status Bits
-#define E1000_RXD_STAT_DD (1 << 0)  // Descriptor Done
+#define E1000_RXD_STAT_DD  (1 << 0) // Descriptor Done
 #define E1000_RXD_STAT_EOP (1 << 1) // End of Packet
-#define E1000_RXD_ERR_CE (1 << 0)   // CRC Error
-#define E1000_RXD_ERR_SE (1 << 1)   // Symbol Error
-#define E1000_RXD_ERR_SEQ (1 << 2)  // Sequence Error
-#define E1000_RXD_ERR_CXE (1 << 3)  // Carrier Extension Error
-#define E1000_RXD_ERR_RXE (1 << 4)  // RX Data Error
+#define E1000_RXD_ERR_CE   (1 << 0) // CRC Error
+#define E1000_RXD_ERR_SE   (1 << 1) // Symbol Error
+#define E1000_RXD_ERR_SEQ  (1 << 2) // Sequence Error
+#define E1000_RXD_ERR_CXE  (1 << 3) // Carrier Extension Error
+#define E1000_RXD_ERR_RXE  (1 << 4) // RX Data Error
 
 // TX Descriptor Command Bits
-#define E1000_TXD_CMD_EOP (1 << 0)  // End of Packet
+#define E1000_TXD_CMD_EOP  (1 << 0) // End of Packet
 #define E1000_TXD_CMD_IFCS (1 << 1) // Insert FCS
-#define E1000_TXD_CMD_RS (1 << 3)   // Report Status
+#define E1000_TXD_CMD_RS   (1 << 3) // Report Status
 
 // TX Descriptor Status Bits
 #define E1000_TXD_STAT_DD (1 << 0) // Descriptor Done
 
 // Constants
-#define E1000_NUM_RX_DESC 32
-#define E1000_NUM_TX_DESC 32
+#define E1000_NUM_RX_DESC    32
+#define E1000_NUM_TX_DESC    32
 #define E1000_RX_BUFFER_SIZE 2048
 #define E1000_TX_BUFFER_SIZE 2048
-#define E1000_MTU 1500
+#define E1000_MTU            1500
 
 #include "cp_kernel.h"
 
@@ -92,37 +92,40 @@ struct e1000_rx_desc {
     uint64_t buffer_addr;
     uint16_t length;
     uint16_t checksum;
-    uint8_t status;
-    uint8_t errors;
+    uint8_t  status;
+    uint8_t  errors;
     uint16_t special;
 } __attribute__((packed));
 
 // TX Descriptor Structure
 struct e1000_tx_desc {
     uint64_t buffer_addr;
     uint16_t length;
-    uint8_t cso;
-    uint8_t cmd;
-    uint8_t status;
-    uint8_t css;
+    uint8_t  cso;
+    uint8_t  cmd;
+    uint8_t  status;
+    uint8_t  css;
     uint16_t special;
 } __attribute__((packed));
 
 // E1000 Device Structure
-typedef struct e1000_device{
-    void *mmio_base;
-    uint8_t mac[6];
+typedef struct e1000_device {
+    void    *mmio_base;
+    uint8_t  mac[6];
     uint32_t mtu;
 
     // RX descriptors and buffers
     struct e1000_rx_desc *rx_descs;
-    void *rx_buffers[E1000_NUM_RX_DESC];
-    uint16_t rx_tail;
+    void                 *rx_buffers[E1000_NUM_RX_DESC];
+    uint16_t              rx_tail;
 
     // TX descriptors and buffers
     struct e1000_tx_desc *tx_descs;
-    void *tx_buffers[E1000_NUM_TX_DESC];
-    uint16_t tx_head;
-    uint16_t tx_tail;
+    void                 *tx_buffers[E1000_NUM_TX_DESC];
+    uint16_t              tx_head;
+    uint16_t              tx_tail;
 } e1000_device_t;
 
+bool    e1000_has_packets(e1000_device_t *dev);
+errno_t e1000_send(void *dev_desc, void *data, uint32_t len);
+errno_t e1000_receive(void *dev_desc, void *buffer, uint32_t buffer_size);