Update the Zumo and 3pi+ example code.

Author: pdg137

default.nix

@@ -2,7 +2,7 @@ let
 
   # This date is used to identify releases.  It gets baked into the filenames,
   # file system timestamps, and `sys.version` in Python.
-  date = "2026-01-27";
+  date = "2026-02-10";
 
   short_date = (builtins.substring 2 2 date) +
     (builtins.substring 5 2 date) + (builtins.substring 8 2 date);
@@ -33,9 +33,12 @@ let
     };
 
     patches = [
+      # Expose traceback info for exceptions, making better error messages possible.
+      # https://github.com/micropython/micropython/pull/11244
       ./mpy-traceback.patch
 
       # ports/rp2/clocks_extra: Set VREG like the SDK: needed for 200 MHz.
+      # https://github.com/micropython/micropython/pull/18739
       ./mpy-vreg.patch
 
        # Change the Pico firmware to use a 1MB USB Mass Storage filesystem.
@@ -100,7 +103,7 @@ in rec {
     board_name = "Raspberry Pi Pico";
     file_name = "pico";
     MICROPY_BOARD = "RPI_PICO";
-    image_size_mb = "2";
+    image_size_mb = 2;
     start_url = "https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html";
     example_code = pkgs.fetchFromGitHub rec {
       owner = "pololu";
@@ -115,27 +118,29 @@ in rec {
     board_name = "Pololu 3pi+ 2040 Robot";
     file_name = "pololu-3pi-2040-robot";
     MICROPY_BOARD = "POLOLU_3PI_2040_ROBOT";
-    image_size_mb = "16";
+    image_size_mb = 16;
     start_url = "https://www.pololu.com/3pi/start";
     example_code = pkgs.fetchFromGitHub rec {
       owner = "pololu";
       repo = "pololu-3pi-2040-robot";
-      rev = "6ddb719da080c21d9d1fb03e9f92007a12848f24";  # 2024-01-16
-      hash = "sha256-KcT2ChRHVFUHAa1h+B75kmP1wDPcyP1cxVF3IsEllxU=";
+      rev = "3eaee7e247a2acf4d2875c766ccaec36881e3ac0";  # 2026-02-09
+      name = "${repo}-${rev}";
+      hash = "sha256-Q63pdnYCjtHLaY0Z33+w0K+INq7i9IVQFTVny0TewSs=";
     };
   };
 
   pololu-zumo-2040-robot = board {
     board_name = "Pololu Zumo 2040 Robot";
     file_name = "pololu-zumo-2040-robot";
     MICROPY_BOARD = "POLOLU_ZUMO_2040_ROBOT";
-    image_size_mb = "16";
+    image_size_mb = 16;
     start_url = "https://www.pololu.com/zumo/start";
     example_code = pkgs.fetchFromGitHub rec {
       owner = "pololu";
       repo = "zumo-2040-robot";
-      rev = "7bf996d4aa4180349538ab3c64980621930f6623";  # 2024-01-16
-      hash = "sha256-V+vFeZ82soP77lXwHTVZks7a2DvdbjIJckPnrViBgCE=";
+      rev = "a530761b51241c4bd23a95b4065b5d113c7f6a23";  # 2026-02-10
+      name = "${repo}-${rev}";
+      hash = "sha256-Dfe9zugGT43uN+gx3hXQaa2l/TR+S/YAaiDrdFpQOWA=";
     };
   };
 

mpy-vreg.patch

@@ -1,21 +1,21 @@
-From 7bdb2682794378cace9fe126d3145038fe681eb7 Mon Sep 17 00:00:00 2001
+From caa5430c35ec318ee4c1af1fa2225a40bfa1da8e Mon Sep 17 00:00:00 2001
 From: "David (Pololu)" <dev-david@pololu.com>
 Date: Tue, 27 Jan 2026 10:56:36 -0800
-Subject: [PATCH] ports/rp2/clocks_extra: Set VREG like the SDK: needed for 200
+Subject: [PATCH] rp2/clocks_extra: Set VREG like the SDK does: needed for 200
  MHz.
 
 The RP2040 now supports running at 200 MHz, but the datasheet says
 that speed requires an elevated core supply of 1.15 V.  The SDK
 implements that in runtime_clocks_init, but we do not call that
-function becausde we override it in clocks_extra.c.
+function because we override it in clocks_extra.c.
 
 Signed-off-by: David (Pololu) <dev-david@pololu.com>
 ---
  ports/rp2/clocks_extra.c | 8 ++++++++
  1 file changed, 8 insertions(+)
 
 diff --git a/ports/rp2/clocks_extra.c b/ports/rp2/clocks_extra.c
-index ab3e6261f..b38452932 100644
+index ab3e6261f..db3643975 100644
 --- a/ports/rp2/clocks_extra.c
 +++ b/ports/rp2/clocks_extra.c
 @@ -14,6 +14,7 @@
@@ -30,12 +30,12 @@ index ab3e6261f..b38452932 100644
          XOSC_HZ,
          XOSC_HZ);
 
-+#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
++    #if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
 +    if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
 +        vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
 +        busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
 +    }
-+#endif
++    #endif
 +
      /// \tag::configure_clk_sys[]
      // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz