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Lore0599Lore0599
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hw: Include EnMulticast in RouteCfg and extend floogen to support mcast
1 parent e516758 commit a86e8b3

13 files changed

+40
-108
lines changed

‎Bender.yml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,6 @@ sources:
3838
- hw/floo_reduction_sync.sv
3939
- hw/floo_route_xymask.sv
4040
- hw/floo_mask_extract.sv
41-
# - hw/floo_mask_translation.sv
4241
# Level 2
4342
- hw/floo_route_select.sv
4443
- hw/floo_route_comp.sv

‎floogen/model/router.py

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,15 @@ def tree_int_to_tuple(cls, v):
4646
return (v,)
4747
return v
4848

49+
@field_validator("xy_id_offset", mode="before")
50+
@classmethod
51+
def dict_to_coord_obj(cls, v):
52+
"""Convert dict to Coord object."""
53+
match v:
54+
case None:
55+
return None
56+
case {"x": x, "y": y}:
57+
return Coord(x=x, y=y)
4958

5059
class Router(BaseModel, ABC):
5160
"""Abstract router class of an actual router"""

‎floogen/model/routing.py

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -451,6 +451,7 @@ class Routing(BaseModel):
451451
rob_idx_bits: int = 1
452452
port_id_bits: int = 1
453453
num_vc_id_bits: int = 0
454+
en_multicast: bool = False
454455

455456
@field_validator("route_algo", mode="before")
456457
@classmethod
@@ -520,6 +521,10 @@ def render_hdr_typedef(self, network_type) -> str:
520521
ch_type = "axi_ch_e" if network_type == "axi" else "nw_ch_e"
521522

522523
if self.num_vc_id_bits == 0:
524+
if self.en_multicast:
525+
return (
526+
f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t,"
527+
f"id_t, collect_comm_e)")
523528
return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t)"
524529
return f"`FLOO_TYPEDEF_VC_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t, vc_id_t)"
525530

@@ -535,5 +540,6 @@ def render_route_cfg(self, name) -> str:
535540
self.route_algo == RouteAlgo.ID and not self.use_id_table else 0,
536541
"NumSamRules": len(self.sam),
537542
"NumRoutes": self.num_endpoints if self.route_algo == RouteAlgo.SRC else 0,
543+
"EnMultiCast": bool_to_sv(self.en_multicast)
538544
}
539545
return sv_param_decl(name, sv_struct_render(fields), dtype="route_cfg_t")

‎hw/floo_axi_chimney.sv

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,6 @@ module floo_axi_chimney #(
2626
/// Every atomic transactions needs to have a unique ID
2727
/// and one ID is reserved for non-atomic transactions
2828
parameter int unsigned MaxAtomicTxns = 1,
29-
/// Enable multicast feature
30-
parameter bit EnMultiCast = 1'b0,
3129
/// Node ID type for routing
3230
parameter type id_t = logic,
3331
/// RoB index type for reordering.
@@ -199,7 +197,7 @@ module floo_axi_chimney #(
199197
`AXI_ASSIGN_RESP_STRUCT(axi_in_rsp_o, axi_rsp_out)
200198

201199
// Extract the multicast mask bits from the AXI user bits
202-
if (EnMultiCast) begin : gen_mask
200+
if (RouteCfg.EnMultiCast) begin : gen_mask
203201
user_struct_t user;
204202
assign user = axi_in_req_i.aw.user;
205203
assign axi_req_in_mask = user.mcast_mask;
@@ -233,7 +231,7 @@ module floo_axi_chimney #(
233231
.valid_o ( axi_ar_queue_valid_out ),
234232
.ready_i ( axi_ar_queue_ready_in )
235233
);
236-
if (EnMultiCast) begin : gen_mask_cuts
234+
if (RouteCfg.EnMultiCast) begin : gen_mask_cuts
237235
spill_register #(
238236
.T (logic [AxiCfg.UserWidth-1:0])
239237
) i_usermask_queue (
@@ -487,8 +485,7 @@ module floo_axi_chimney #(
487485
.id_t (id_t),
488486
.addr_t (axi_addr_t),
489487
.addr_rule_t(sam_rule_t),
490-
.mask_sel_t (mask_sel_t),
491-
.EnMultiCast(EnMultiCast)
488+
.mask_sel_t (mask_sel_t)
492489
) i_floo_id_translation (
493490
.clk_i,
494491
.rst_ni,
@@ -520,7 +517,7 @@ module floo_axi_chimney #(
520517
`FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out &&
521518
axi_aw_queue_ready_in, '0)
522519

523-
if (EnMultiCast) begin : gen_mcast
520+
if (RouteCfg.EnMultiCast) begin : gen_mcast
524521
localparam int unsigned AddrWidth = $bits(axi_addr_t);
525522
axi_addr_t [NumAxiChannels-1:0] x_addr_mask;
526523
axi_addr_t [NumAxiChannels-1:0] y_addr_mask;
@@ -779,7 +776,6 @@ module floo_axi_chimney #(
779776
.MaxUniqueIds ( ChimneyCfg.MaxUniqueIds ),
780777
.AtopSupport ( AtopSupport ),
781778
.MaxAtomicTxns ( MaxAtomicTxns ),
782-
.EnMultiCast ( EnMultiCast ),
783779
.Sam ( Sam ),
784780
.buf_t ( meta_buf_t ),
785781
.axi_in_req_t ( axi_req_t ),

‎hw/floo_id_translation.sv

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
/// or a simple offset based translation.
1313
module floo_id_translation #(
1414
/// The route config
15-
parameter floo_pkg::route_cfg_t RouteCfg = '0,
15+
parameter floo_pkg::route_cfg_t RouteCfg = floo_pkg::RouteDefaultCfg,
1616
/// The type of the ID
1717
parameter type id_t = logic,
1818
/// The type of the IDX field in the address rule
@@ -24,8 +24,7 @@ module floo_id_translation #(
2424
/// The System Address Map
2525
parameter addr_rule_t [RouteCfg.NumSamRules-1:0] Sam,
2626
/// The type of the offset + len to identify which bits in the address can be masked
27-
parameter type mask_sel_t = logic,
28-
parameter bit EnMultiCast = 1'b0
27+
parameter type mask_sel_t = logic
2928
) (
3029
input logic clk_i, // Only used for assertions
3130
input logic rst_ni, // Only used for assertions
@@ -66,7 +65,7 @@ module floo_id_translation #(
6665

6766
`ASSERT(DecodeError, !(dec_error && valid_i))
6867

69-
if (EnMultiCast) begin: gen_mcast_id_mask
68+
if (RouteCfg.EnMultiCast) begin: gen_mcast_id_mask
7069
assign mask_addr_x_o = idx_out.mask_x;
7170
assign mask_addr_y_o = idx_out.mask_y;
7271
assign id_o = idx_out.id;

‎hw/floo_mask_translation.sv

Lines changed: 0 additions & 70 deletions
This file was deleted.

‎hw/floo_meta_buffer.sv

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,6 @@ module floo_meta_buffer #(
2424
parameter bit AtopSupport = 1'b1,
2525
/// Number of outstanding atomic requests
2626
parameter int MaxAtomicTxns = 32'd1,
27-
/// Enable multicast support
28-
parameter bit EnMultiCast = 1'b0,
2927
/// AXI in request channel
3028
parameter type axi_in_req_t = logic,
3129
/// AXI in response channel
@@ -218,7 +216,7 @@ module floo_meta_buffer #(
218216

219217
// NoC addr/mask to AXI addr/mask conversion
220218
localparam int unsigned AddrWidth = $bits(addr_t);
221-
if (EnMultiCast && RouteCfg.UseIdTable &&
219+
if (RouteCfg.EnMultiCast && RouteCfg.UseIdTable &&
222220
(RouteCfg.RouteAlgo == floo_pkg::XYRouting))
223221
begin : gen_mcast_table_conversion
224222
id_t out, in_mask, in_id;
@@ -237,8 +235,7 @@ module floo_meta_buffer #(
237235
.id_t (id_t),
238236
.addr_t (addr_t),
239237
.addr_rule_t(sam_rule_t),
240-
.mask_sel_t (mask_sel_t),
241-
.EnMultiCast(EnMultiCast)
238+
.mask_sel_t (mask_sel_t)
242239
) i_floo_id_translation (
243240
.clk_i,
244241
.rst_ni,

‎hw/floo_nw_chimney.sv

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,6 @@ module floo_nw_chimney #(
3030
/// Every atomic transactions needs to have a unique ID
3131
/// and one ID is reserved for non-atomic transactions
3232
parameter int unsigned MaxAtomicTxns = 1,
33-
// TODO(fischeti): Move to RouteCfg
34-
parameter bit EnMultiCast = 1'b0,
3533
/// Node ID type for routing
3634
parameter type id_t = logic,
3735
/// RoB index type for reordering.
@@ -258,7 +256,7 @@ module floo_nw_chimney #(
258256
`AXI_ASSIGN_RESP_STRUCT(axi_narrow_in_rsp_o, axi_narrow_rsp_out)
259257

260258
// Extract the multicast mask bits from the AXI user bits
261-
if (EnMultiCast) begin : gen_mask
259+
if (RouteCfg.EnMultiCast) begin : gen_mask
262260
user_struct_t user;
263261
assign user = axi_narrow_in_req_i.aw.user;
264262
// TODO(lleone): Check subfield name is `mcast_mask`
@@ -294,7 +292,7 @@ module floo_nw_chimney #(
294292
.ready_i ( axi_narrow_ar_queue_ready_in )
295293
);
296294

297-
if (EnMultiCast) begin : gen_mask_cuts
295+
if (RouteCfg.EnMultiCast) begin : gen_mask_cuts
298296
spill_register #(
299297
.T (user_mask_t)
300298
) i_narrow_usermask_queue (
@@ -349,7 +347,7 @@ module floo_nw_chimney #(
349347
`AXI_ASSIGN_REQ_STRUCT(axi_wide_req_in, axi_wide_in_req_i)
350348
`AXI_ASSIGN_RESP_STRUCT(axi_wide_in_rsp_o, axi_wide_rsp_out)
351349

352-
if (EnMultiCast) begin : gen_mask
350+
if (RouteCfg.EnMultiCast) begin : gen_mask
353351
assign axi_wide_req_in_mask = axi_wide_in_req_i.aw.user;
354352
end else begin : gen_no_mask
355353
assign axi_wide_req_in_mask = '0;
@@ -382,7 +380,7 @@ module floo_nw_chimney #(
382380
.ready_i ( axi_wide_ar_queue_ready_in )
383381
);
384382

385-
if (EnMultiCast) begin : gen_mask_cuts
383+
if (RouteCfg.EnMultiCast) begin : gen_mask_cuts
386384
spill_register #(
387385
.T (user_mask_t)
388386
) i_wide_usermask_queue (
@@ -803,8 +801,7 @@ module floo_nw_chimney #(
803801
.id_t (id_t),
804802
.addr_t (axi_addr_t),
805803
.addr_rule_t(sam_rule_t),
806-
.mask_sel_t (mask_sel_t),
807-
.EnMultiCast(EnMultiCast)
804+
.mask_sel_t (mask_sel_t)
808805
) i_floo_id_translation (
809806
.clk_i,
810807
.rst_ni,
@@ -842,7 +839,7 @@ module floo_nw_chimney #(
842839
`FFL(wide_aw_id_q, dst_id[WideAw], axi_wide_aw_queue_valid_out &&
843840
axi_wide_aw_queue_ready_in, '0)
844841

845-
if (EnMultiCast) begin : gen_mcast
842+
if (RouteCfg.EnMultiCast) begin : gen_mcast
846843
localparam int unsigned AddrWidth = $bits(axi_addr_t);
847844
axi_addr_t [NumNWAxiChannels-1:0] x_addr_mask;
848845
axi_addr_t [NumNWAxiChannels-1:0] y_addr_mask;
@@ -1292,7 +1289,6 @@ module floo_nw_chimney #(
12921289
.MaxUniqueIds ( ChimneyCfgN.MaxUniqueIds ),
12931290
.AtopSupport ( AtopSupport ),
12941291
.MaxAtomicTxns ( MaxAtomicTxns ),
1295-
.EnMultiCast ( EnMultiCast ),
12961292
.Sam ( Sam ),
12971293
.buf_t ( narrow_meta_buf_t ),
12981294
.axi_in_req_t ( axi_narrow_req_t ),
@@ -1345,7 +1341,6 @@ module floo_nw_chimney #(
13451341
.MaxUniqueIds ( ChimneyCfgW.MaxUniqueIds ),
13461342
.AtopSupport ( 1'b0 ),
13471343
.MaxAtomicTxns ( '0 ),
1348-
.EnMultiCast ( EnMultiCast ),
13491344
.Sam ( Sam ),
13501345
.buf_t ( wide_meta_buf_t ),
13511346
.axi_in_req_t ( axi_wide_req_t ),

‎hw/floo_pkg.sv

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,8 @@ package floo_pkg;
155155
/// The number of routes for every routing table,
156156
/// Only used if `RouteAlgo == SourceRouting`
157157
int unsigned NumRoutes;
158+
/// Whether to enable the multicast feature in the NoC
159+
bit EnMultiCast;
158160
} route_cfg_t;
159161

160162
/// Configuration for the network interface (chimney)
@@ -217,7 +219,8 @@ package floo_pkg;
217219
XYAddrOffsetY: 0,
218220
IdAddrOffset: 0,
219221
NumSamRules: 0,
220-
NumRoutes: 0
222+
NumRoutes: 0,
223+
EnMultiCast: 1'b0
221224
};
222225

223226
/// The AXI channel to link mapping in a single-AXI network interface

‎hw/floo_route_comp.sv

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@ module floo_route_comp
1212
/// The route config
1313
parameter floo_pkg::route_cfg_t RouteCfg = '0,
1414
parameter bit UseIdTable = RouteCfg.UseIdTable,
15-
parameter bit EnMultiCast = 1'b0,
1615
parameter type id_t = logic,
1716
/// The type of the address
1817
parameter type addr_t = logic,
@@ -74,7 +73,7 @@ module floo_route_comp
7473
.en_default_idx_i ( 1'b0 ),
7574
.default_idx_i ( '0 )
7675
);
77-
if (EnMultiCast && RouteCfg.UseIdTable &&
76+
if (RouteCfg.EnMultiCast && RouteCfg.UseIdTable &&
7877
(RouteCfg.RouteAlgo == floo_pkg::XYRouting))
7978
begin : gen_mcast_mask
8079
floo_mask_decode #(
@@ -107,7 +106,7 @@ module floo_route_comp
107106
assign id_o.port_id = '0;
108107
assign id_o.x = addr_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)];
109108
assign id_o.y = addr_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)];
110-
if(EnMultiCast) begin : gen_mcast_mask
109+
if(RouteCfg.EnMultiCast) begin : gen_mcast_mask
111110
assign mask_o.x = mask_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)];
112111
assign mask_o.y = mask_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)];
113112
assign mask_o.port_id = '0;

‎hw/floo_router.sv

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,8 @@ module floo_router
299299
if (NoLoopback) begin: gen_no_loopback_assert
300300
for (genvar in = 0; in < NumInput; in++) begin : gen_input
301301
for (genvar v = 0; v < NumVirtChannels; v++) begin : gen_virt
302-
`ASSERT(NoLoopback, !(in_valid[in][v] && route_mask[in][v][in] && (in_data[in][v].hdr.commtype == Unicast)))
302+
`ASSERT(NoLoopback, !(in_valid[in][v] && route_mask[in][v][in] &&
303+
(in_data[in][v].hdr.commtype == Unicast)))
303304
end
304305
end
305306
end

‎hw/tb/tb_floo_axi_chimney.sv

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,7 @@ module tb_floo_axi_chimney;
2626
typedef logic [1:0] x_bits_t;
2727
typedef logic [1:0] y_bits_t;
2828
`FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic)
29-
`FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic, id_t,
30-
floo_pkg::collect_comm_e)
29+
`FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic)
3130
`FLOO_TYPEDEF_AXI_FROM_CFG(axi, floo_test_pkg::AxiCfg)
3231
`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, floo_test_pkg::AxiCfg, hdr_t)
3332
`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp)

‎hw/tb/tb_floo_nw_chimney.sv

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,7 @@ module tb_floo_nw_chimney;
5050
typedef logic [1:0] y_bits_t;
5151
`FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic)
5252
// `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic)
53-
`FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic, id_t,
54-
floo_pkg::collect_comm_e)
53+
`FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic)
5554
`FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN)
5655
`FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW)
5756
`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in,

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