How can I write the easiest testbench for my floogen files

[NorrisChina]

Dear Handsome,

I am trying to use floogen to generate the easiest network of 2 cores and 2 routers, core0->router0->router1->core1, with this yml:

name: core2router2
description: "NoC with Two Cores and Two Routers in a Linear Topology"
network_type: "narrow-wide"

routing:
  route_algo: "ID"
  use_id_table: true

protocols:
  - name: "narrow_in"
    type: "narrow"
    protocol: "AXI4"
    data_width: 64
    addr_width: 48
    id_width: 4
    user_width: 1
  - name: "narrow_out"
    type: "narrow"
    protocol: "AXI4"
    data_width: 64
    addr_width: 48
    id_width: 2
    user_width: 1
  - name: "wide_in"
    type: "wide"
    protocol: "AXI4"
    data_width: 512
    addr_width: 48
    id_width: 3
    user_width: 1
  - name: "wide_out"
    type: "wide"
    protocol: "AXI4"
    data_width: 512
    addr_width: 48
    id_width: 1
    user_width: 1

endpoints:
  - name: "core0"
    addr_range:
      base: 0x0000_1000_0000
      size: 0x0000_0004_0000
    mgr_port_protocol:
      - "narrow_in"
      - "wide_in"
    sbr_port_protocol:
      - "narrow_out"
      - "wide_out"

  - name: "core1"
    addr_range:
      base: 0x0000_2000_0000
      size: 0x0000_0004_0000
    mgr_port_protocol:
      - "narrow_in"
      - "wide_in"
    sbr_port_protocol:
      - "narrow_out"
      - "wide_out"

routers:
  - name: "Router0"
  - name: "Router1"

connections:
  - src: "core0"
    dst: "Router0"
  - src: "Router0"
    dst: "Router1"
  - src: "Router1"
    dst: "core1"

When I wrote my test bench for this noc.sv, when I debugged, I found there were four comps generated automatically with the network initialization. In floo_nw_chimney.sv line 647, I got gen_route_comp[0][2][3][7], when I checked the floopkg.sv line 88-100, it is the NarrowAw(0), NarrowAr(2), WideAr(3), WideAw(7), they are open automatically.

But in my testbench, I only want to use the narrow address write to send write one data from core0 to core1, by this

    core0_narrow_in_req.aw.addr = 48'h000020000100;
    core0_narrow_in_req.aw.id = 4'h1;
    core0_narrow_in_req.aw.len = 8'h0;  // Single transfer
    core0_narrow_in_req.aw.size = 3'b011;  // 8 bytes
    core0_narrow_in_req.aw.burst = 2'b01;  // INCR
    core0_narrow_in_req.aw_valid = 1'b1;

    // Wait for AW ready
    while (!core0_narrow_in_rsp.aw_ready) @(posedge clk_i);
    @(posedge clk_i);
    core0_narrow_in_req.aw_valid = 1'b0;

    // Setup write data channel
    core0_narrow_in_req.w.data = 64'b0101010101010101;
    core0_narrow_in_req.w.strb = 8'hFF;
    core0_narrow_in_req.w.last = 1'b1;
    core0_narrow_in_req.w_valid = 1'b1;

There are lots of errors saying my gen_route_comp[0][2][3][7] is the wrong address as I did not set it and use it.

How can I write the correct testbench to control the network? and it seems my core1 did not receive any message from my core0.

Can I get any examples for the testbench of this project? Even in the "tb_floo_axi_mesh.sv" I did not see any signal input for this network. How can I write any AXI input for this generated_floonoc.sv by floogen?

[fischeti]

I think the problem is that if you tie the unused signals to '0, then the address decoder inside the chimney will complain that this is not a valid address, even if the valid signal is not applied. The best way would be make the assertion depend on the valid signal as well. I currently don't have the time to look into this, but feel free to open a PR.

The other solution how to fix is is to apply default address that is in the system address map. Or you can also use the axi_chimney variants, which only have a single AXI port

[NorrisChina]

I think the problem is that if you tie the unused signals to '0, then the address decoder inside the chimney will complain that this is not a valid address, even if the valid signal is not applied. The best way would be make the assertion depend on the valid signal as well. I currently don't have the time to look into this, but feel free to open a PR.

The other solution how to fix is is to apply default address that is in the system address map. Or you can also use the axi_chimney variants, which only have a single AXI port

I changed this line change the NoLoopback from 1 into 0:
1️⃣

parameter bit          NoLoopback       = 1'b0  // in floo_router.sv

2️⃣I swap the floogen.py connection for my module.sv

//  assign Router0_to_core0_ni_req = Router0_req_out[0];
//  assign Router0_to_Router1_req = Router0_req_out[1];
  
  assign Router0_to_core0_ni_req = Router0_req_out[1];//swap
  assign Router0_to_Router1_req = Router0_req_out[0];


//  assign Router1_to_Router0_req = Router1_req_out[0];
//  assign Router1_to_core1_ni_req = Router1_req_out[1];
 
  assign Router1_to_Router0_req = Router1_req_out[1];//swap
  assign Router1_to_core1_ni_req = Router1_req_out[0];

Then I can receive my core0 message from core1_axi_out.

I am not sure why, but when I do like this, it is working...

[NorrisChina]

[NorrisChina]