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4 files changed +717
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lines changed Original file line number Diff line number Diff line change @@ -41,6 +41,8 @@ synopsys_dc:
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fuse_xsim :
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stage : build
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+ allow_failure : true
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+ timeout : 5 minutes
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script :
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- bender sources
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- /usr/local/anaconda3/bin/python3 -m pip install fusesoc --user
Original file line number Diff line number Diff line change @@ -65,7 +65,7 @@ sources:
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- src/axi_serializer.sv
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- src/axi_slave_compare.sv
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- src/axi_throttle.sv
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- - src/axi_to_mem .sv
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+ - src/axi_to_detailed_mem .sv
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# Level 3
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- src/axi_cdc.sv
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- src/axi_demux.sv
@@ -76,13 +76,14 @@ sources:
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- src/axi_lfsr.sv
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- src/axi_multicut.sv
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- src/axi_to_axi_lite.sv
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- - src/axi_to_mem_banked.sv
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- - src/axi_to_mem_interleaved.sv
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- - src/axi_to_mem_split.sv
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+ - src/axi_to_mem.sv
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# Level 4
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- src/axi_iw_converter.sv
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- src/axi_lite_xbar.sv
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- src/axi_xbar.sv
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+ - src/axi_to_mem_banked.sv
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+ - src/axi_to_mem_interleaved.sv
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+ - src/axi_to_mem_split.sv
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# Level 5
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- src/axi_xp.sv
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