Release v0.39.10

Author: imchenwu

Bender.yml

@@ -2,15 +2,17 @@ package:
   name: axi
   authors:
     # Alphabetically ordered by last name (maintainers first)
-    - "Thomas Benz <tbenz@iis.ee.ethz.ch>" # current maintainer
-    - "Michael Rogenmoser <michaero@iis.ee.ethz.ch>" # current maintainer
+    - "Chen Wu <chenwu@iis.ee.ethz.ch>" # current maintainer
+    - "Niccolo Giuliani <niccolo.giuliani@chips.it>" # current maintainer
+    - "Thomas Benz <tbenz@iis.ee.ethz.ch>"
     - "Matheus Cavalcante <matheusd@iis.ee.ethz.ch>"
     - "Tim Fischer <fischeti@iis.ee.ethz.ch>"
     - "Noah Huetter <huettern@ethz.ch>"
     - "Cyril Koenig <cykoenig@iis.ee.ethz.ch>"
     - "Andreas Kurth <akurth@iis.ee.ethz.ch>"
     - "Stefan Mach <smach@iis.ee.ethz.ch>"
     - "Samuel Riedel <sriedel@iis.ee.ethz.ch>"
+    - "Michael Rogenmoser <michaero@iis.ee.ethz.ch>"
     - "Wolfgang Rönninger <wroennin@iis.ee.ethz.ch>"
     - "Paul Scheffler <paulsc@iis.ee.ethz.ch>"
     - "Fabian Schuiki <fschuiki@iis.ee.ethz.ch>"

CHANGELOG.md

@@ -7,6 +7,30 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+## 0.39.10 - 2026-06-19
+
+### Added
+- Add core file entries required for the FuseSoC package database. #404
+- `axi_demux_id_counters`: Separate into its own module and add port. #406
+- Add `DECL` macros to be used in the parameter port list. #413
+- Add GitHub Action for Verilator lint and yosys-slang elaboration. #414
+
+### Fixed
+- Use XSIM define to remove all default disable blocks under `src`. #391
+- `axi_fifo_delay_dyn`: Correct FF macro termination. #403
+- `axi_lite_mailbox`: Fix `wstrb` AXI violation. #412
+- treewide: Fix various lint issues. #416
+- `tb_axi_xbar`: Fix queue format specifier. #417
+- `axi_to_detailed_mem_intf`: Fix user/id width. #418
+- `axi_sim_mem`, `tb_axi_xbar`: Fix elaboration issues surfaced by Verilator/yosys-slang. #414
+
+### Changed
+- `axi_xbar_unmuxed`: Exclude multidimensional interface code from Genus targets. #405
+- `axi_xbar`: Remove redundant assertions. #407
+- `axi_id_remap`: Enable non-atop writes when reads are stalled and vice versa #409
+- Replace memora with GitLab-native artifacts and rules in CI. #424
+
+
 ## 0.39.9 - 2025-11-21
 
 ### Added

README.md

@@ -30,6 +30,7 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_delayer`](src/axi_delayer.sv)                         | Synthesizable module which can (randomly) delays AXI channels.                                       |                                  |
 | [`axi_demux_simple`](src/axi_demux_simple.sv)               | Demux without spill registers.                                                                       | [Doc](doc/axi_demux.md)          |
 | [`axi_demux`](src/axi_demux.sv)                             | Demultiplexes an AXI bus from one slave port to multiple master ports.                               | [Doc](doc/axi_demux.md)          |
+| [`axi_demux_id_counters`](src/axi_demux_id_counters.sv)     | ID counters used by `axi_demux` to track outstanding transactions.                                   |                                  |
 | [`axi_dw_converter`](src/axi_dw_converter.sv)               | A data width converter between AXI interfaces of any data width.                                     |                                  |
 | [`axi_dw_downsizer`](src/axi_dw_downsizer.sv)               | A data width converter between a wide AXI master and a narrower AXI slave.                           |                                  |
 | [`axi_dw_upsizer`](src/axi_dw_upsizer.sv)                   | A data width converter between a narrow AXI master and a wider AXI slave.                            |                                  |
@@ -64,7 +65,6 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_rw_join`](src/axi_rw_join.sv)                         | Joins a read and a write slave into one single read / write master.                                  |                                  |
 | [`axi_rw_split`](src/axi_rw_split.sv)                       | Splits a single read / write slave into one read and one write master.                               |                                  |
 | [`axi_serializer`](src/axi_serializer.sv)                   | Serializes transactions with different IDs to the same ID.                                           |                                  |
-| [`axi_slave_compare`](src/axi_slave_compare.sv)             | Compares two slave devices.                                                                          |                                  |
 | [`axi_throttle`](src/axi_throttle.sv)                       | Limits the maximum number of outstanding transfers sent to the downstream logic.                     |                                  |
 | [`axi_test`](src/axi_test.sv)                               | A set of testbench utilities for AXI interfaces.                                                     |                                  |
 | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv)                 | AXI4 to AXI4-Lite protocol converter.                                                                |                                  |

VERSION

@@ -1 +1 @@
-0.39.9
+0.39.10

axi.core

@@ -1,6 +1,6 @@
 CAPI=2:
 
-name: pulp-platform.org::axi:0.39.9
+name: pulp-platform.org::axi:0.39.10
 description: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.
 license: SHL-0.51