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Merge pull request #198 from pulp-platform/prefix-req-resp-type-params
Prefix `req_t` and `resp_t` type parameters with `axi_`.
2 parents 20311e7 + be15c99 commit 35bcbdb

24 files changed

+346
-339
lines changed

‎CHANGELOG.md

+7
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
1010
### Added
1111

1212
### Changed
13+
- `axi_atop_filter`, `axi_burst_splitter`, `axi_cut`, `axi_delayer`, `axi_demux`, `axi_err_slv`,
14+
`axi_isolate`, `axi_lite_demux`, `axi_lite_mux`, `axi_lite_to_axi`, and `axi_lite_xbar`,
15+
`axi_multicut`, `axi_serializer`, `axi_sim_mem`: Prefix `req_t` and `resp_t` type parameters with
16+
`axi_`. This prevents type collisions in tools that have problems with correct type resolution
17+
and isolation. This change is **backward-incompatible** for all instances of the listed modules
18+
outside this repository. Users must update all instances of the listed modules in their code.
19+
Interface variants are not affected and remain backward-compatible.
1320

1421
### Fixed
1522

‎VERSION

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
0.31.2-dev
1+
0.32.0-dev

‎axi.core

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
CAPI=2:
22

3-
name : pulp-platform.org::axi:0.31.2-dev
3+
name : pulp-platform.org::axi:0.32.0-dev
44

55
filesets:
66
rtl:

‎src/axi_atop_filter.sv

+14-14
Original file line numberDiff line numberDiff line change
@@ -40,22 +40,22 @@ module axi_atop_filter #(
4040
/// Maximum number of in-flight AXI write transactions
4141
parameter int unsigned AxiMaxWriteTxns = 0,
4242
/// AXI request type
43-
parameter type req_t = logic,
43+
parameter type axi_req_t = logic,
4444
/// AXI response type
45-
parameter type resp_t = logic
45+
parameter type axi_resp_t = logic
4646
) (
4747
/// Rising-edge clock of both ports
48-
input logic clk_i,
48+
input logic clk_i,
4949
/// Asynchronous reset, active low
50-
input logic rst_ni,
50+
input logic rst_ni,
5151
/// Slave port request
52-
input req_t slv_req_i,
52+
input axi_req_t slv_req_i,
5353
/// Slave port response
54-
output resp_t slv_resp_o,
54+
output axi_resp_t slv_resp_o,
5555
/// Master port request
56-
output req_t mst_req_o,
56+
output axi_req_t mst_req_o,
5757
/// Master port response
58-
input resp_t mst_resp_i
58+
input axi_resp_t mst_resp_i
5959
);
6060

6161
// Minimum counter width is 2 to detect underflows.
@@ -405,11 +405,11 @@ module axi_atop_filter_intf #(
405405
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
406406
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
407407
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
408-
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
409-
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
408+
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
409+
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
410410

411-
req_t slv_req, mst_req;
412-
resp_t slv_resp, mst_resp;
411+
axi_req_t slv_req, mst_req;
412+
axi_resp_t slv_resp, mst_resp;
413413

414414
`AXI_ASSIGN_TO_REQ(slv_req, slv)
415415
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
@@ -422,8 +422,8 @@ module axi_atop_filter_intf #(
422422
// Maximum number of AXI write bursts outstanding at the same time
423423
.AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),
424424
// AXI request & response type
425-
.req_t ( req_t ),
426-
.resp_t ( resp_t )
425+
.axi_req_t ( axi_req_t ),
426+
.axi_resp_t ( axi_resp_t )
427427
) i_axi_atop_filter (
428428
.clk_i,
429429
.rst_ni,

‎src/axi_burst_splitter.sv

+28-28
Original file line numberDiff line numberDiff line change
@@ -35,19 +35,19 @@ module axi_burst_splitter #(
3535
parameter int unsigned DataWidth = 32'd0,
3636
parameter int unsigned IdWidth = 32'd0,
3737
parameter int unsigned UserWidth = 32'd0,
38-
parameter type req_t = logic,
39-
parameter type resp_t = logic
38+
parameter type axi_req_t = logic,
39+
parameter type axi_resp_t = logic
4040
) (
4141
input logic clk_i,
4242
input logic rst_ni,
4343

4444
// Input / Slave Port
45-
input req_t slv_req_i,
46-
output resp_t slv_resp_o,
45+
input axi_req_t slv_req_i,
46+
output axi_resp_t slv_resp_o,
4747

4848
// Output / Master Port
49-
output req_t mst_req_o,
50-
input resp_t mst_resp_i
49+
output axi_req_t mst_req_o,
50+
input axi_resp_t mst_resp_i
5151
);
5252

5353
typedef logic [AddrWidth-1:0] addr_t;
@@ -62,28 +62,28 @@ module axi_burst_splitter #(
6262
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
6363

6464
// Demultiplex between supported and unsupported transactions.
65-
req_t act_req, unsupported_req;
66-
resp_t act_resp, unsupported_resp;
67-
logic sel_aw_unsupported, sel_ar_unsupported;
65+
axi_req_t act_req, unsupported_req;
66+
axi_resp_t act_resp, unsupported_resp;
67+
logic sel_aw_unsupported, sel_ar_unsupported;
6868
localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns;
6969
axi_demux #(
70-
.AxiIdWidth ( IdWidth ),
71-
.aw_chan_t ( aw_chan_t ),
72-
.w_chan_t ( w_chan_t ),
73-
.b_chan_t ( b_chan_t ),
74-
.ar_chan_t ( ar_chan_t ),
75-
.r_chan_t ( r_chan_t ),
76-
.req_t ( req_t ),
77-
.resp_t ( resp_t ),
78-
.NoMstPorts ( 2 ),
79-
.MaxTrans ( MaxTxns ),
80-
.AxiLookBits ( IdWidth ),
81-
.FallThrough ( 1'b1 ),
82-
.SpillAw ( 1'b0 ),
83-
.SpillW ( 1'b0 ),
84-
.SpillB ( 1'b0 ),
85-
.SpillAr ( 1'b0 ),
86-
.SpillR ( 1'b0 )
70+
.AxiIdWidth ( IdWidth ),
71+
.aw_chan_t ( aw_chan_t ),
72+
.w_chan_t ( w_chan_t ),
73+
.b_chan_t ( b_chan_t ),
74+
.ar_chan_t ( ar_chan_t ),
75+
.r_chan_t ( r_chan_t ),
76+
.axi_req_t ( axi_req_t ),
77+
.axi_resp_t ( axi_resp_t ),
78+
.NoMstPorts ( 2 ),
79+
.MaxTrans ( MaxTxns ),
80+
.AxiLookBits ( IdWidth ),
81+
.FallThrough ( 1'b1 ),
82+
.SpillAw ( 1'b0 ),
83+
.SpillW ( 1'b0 ),
84+
.SpillB ( 1'b0 ),
85+
.SpillAr ( 1'b0 ),
86+
.SpillR ( 1'b0 )
8787
) i_demux_supported_vs_unsupported (
8888
.clk_i,
8989
.rst_ni,
@@ -119,8 +119,8 @@ module axi_burst_splitter #(
119119
// Respond to unsupported transactions with slave errors.
120120
axi_err_slv #(
121121
.AxiIdWidth ( IdWidth ),
122-
.req_t ( req_t ),
123-
.resp_t ( resp_t ),
122+
.axi_req_t ( axi_req_t ),
123+
.axi_resp_t ( axi_resp_t ),
124124
.Resp ( axi_pkg::RESP_SLVERR ),
125125
.ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs.
126126
.MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus.

‎src/axi_cut.sv

+38-38
Original file line numberDiff line numberDiff line change
@@ -19,25 +19,25 @@
1919
/// Breaks all combinatorial paths between its input and output.
2020
module axi_cut #(
2121
// bypass enable
22-
parameter bit Bypass = 1'b0,
22+
parameter bit Bypass = 1'b0,
2323
// AXI channel structs
24-
parameter type aw_chan_t = logic,
25-
parameter type w_chan_t = logic,
26-
parameter type b_chan_t = logic,
27-
parameter type ar_chan_t = logic,
28-
parameter type r_chan_t = logic,
24+
parameter type aw_chan_t = logic,
25+
parameter type w_chan_t = logic,
26+
parameter type b_chan_t = logic,
27+
parameter type ar_chan_t = logic,
28+
parameter type r_chan_t = logic,
2929
// AXI request & response structs
30-
parameter type req_t = logic,
31-
parameter type resp_t = logic
30+
parameter type axi_req_t = logic,
31+
parameter type axi_resp_t = logic
3232
) (
33-
input logic clk_i,
34-
input logic rst_ni,
33+
input logic clk_i,
34+
input logic rst_ni,
3535
// salve port
36-
input req_t slv_req_i,
37-
output resp_t slv_resp_o,
36+
input axi_req_t slv_req_i,
37+
output axi_resp_t slv_resp_o,
3838
// master port
39-
output req_t mst_req_o,
40-
input resp_t mst_resp_i
39+
output axi_req_t mst_req_o,
40+
input axi_resp_t mst_resp_i
4141
);
4242

4343
// a spill register for each channel
@@ -145,11 +145,11 @@ module axi_cut_intf #(
145145
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
146146
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
147147
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
148-
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
149-
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
148+
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
149+
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
150150

151-
req_t slv_req, mst_req;
152-
resp_t slv_resp, mst_resp;
151+
axi_req_t slv_req, mst_req;
152+
axi_resp_t slv_resp, mst_resp;
153153

154154
`AXI_ASSIGN_TO_REQ(slv_req, in)
155155
`AXI_ASSIGN_FROM_RESP(in, slv_resp)
@@ -158,14 +158,14 @@ module axi_cut_intf #(
158158
`AXI_ASSIGN_TO_RESP(mst_resp, out)
159159

160160
axi_cut #(
161-
.Bypass ( BYPASS ),
162-
.aw_chan_t ( aw_chan_t ),
163-
.w_chan_t ( w_chan_t ),
164-
.b_chan_t ( b_chan_t ),
165-
.ar_chan_t ( ar_chan_t ),
166-
.r_chan_t ( r_chan_t ),
167-
.req_t ( req_t ),
168-
.resp_t ( resp_t )
161+
.Bypass ( BYPASS ),
162+
.aw_chan_t ( aw_chan_t ),
163+
.w_chan_t ( w_chan_t ),
164+
.b_chan_t ( b_chan_t ),
165+
.ar_chan_t ( ar_chan_t ),
166+
.r_chan_t ( r_chan_t ),
167+
.axi_req_t ( axi_req_t ),
168+
.axi_resp_t ( axi_resp_t )
169169
) i_axi_cut (
170170
.clk_i,
171171
.rst_ni,
@@ -219,11 +219,11 @@ module axi_lite_cut_intf #(
219219
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
220220
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
221221
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
222-
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
223-
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
222+
`AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
223+
`AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
224224

225-
req_t slv_req, mst_req;
226-
resp_t slv_resp, mst_resp;
225+
axi_req_t slv_req, mst_req;
226+
axi_resp_t slv_resp, mst_resp;
227227

228228
`AXI_LITE_ASSIGN_TO_REQ(slv_req, in)
229229
`AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp)
@@ -232,14 +232,14 @@ module axi_lite_cut_intf #(
232232
`AXI_LITE_ASSIGN_TO_RESP(mst_resp, out)
233233

234234
axi_cut #(
235-
.Bypass ( BYPASS ),
236-
.aw_chan_t ( aw_chan_t ),
237-
.w_chan_t ( w_chan_t ),
238-
.b_chan_t ( b_chan_t ),
239-
.ar_chan_t ( ar_chan_t ),
240-
.r_chan_t ( r_chan_t ),
241-
.req_t ( req_t ),
242-
.resp_t ( resp_t )
235+
.Bypass ( BYPASS ),
236+
.aw_chan_t ( aw_chan_t ),
237+
.w_chan_t ( w_chan_t ),
238+
.b_chan_t ( b_chan_t ),
239+
.ar_chan_t ( ar_chan_t ),
240+
.r_chan_t ( r_chan_t ),
241+
.axi_req_t ( axi_req_t ),
242+
.axi_resp_t ( axi_resp_t )
243243
) i_axi_cut (
244244
.clk_i,
245245
.rst_ni,

‎src/axi_delayer.sv

+19-19
Original file line numberDiff line numberDiff line change
@@ -16,28 +16,28 @@
1616
/// Synthesizable module that (randomly) delays AXI channels.
1717
module axi_delayer #(
1818
// AXI channel types
19-
parameter type aw_chan_t = logic,
20-
parameter type w_chan_t = logic,
21-
parameter type b_chan_t = logic,
22-
parameter type ar_chan_t = logic,
23-
parameter type r_chan_t = logic,
19+
parameter type aw_chan_t = logic,
20+
parameter type w_chan_t = logic,
21+
parameter type b_chan_t = logic,
22+
parameter type ar_chan_t = logic,
23+
parameter type r_chan_t = logic,
2424
// AXI request & response types
25-
parameter type req_t = logic,
26-
parameter type resp_t = logic,
25+
parameter type axi_req_t = logic,
26+
parameter type axi_resp_t = logic,
2727
// delay parameters
2828
parameter bit StallRandomInput = 0,
2929
parameter bit StallRandomOutput = 0,
3030
parameter int unsigned FixedDelayInput = 1,
3131
parameter int unsigned FixedDelayOutput = 1
3232
) (
33-
input logic clk_i, // Clock
34-
input logic rst_ni, // Asynchronous reset active low
33+
input logic clk_i, // Clock
34+
input logic rst_ni, // Asynchronous reset active low
3535
// slave port
36-
input req_t slv_req_i,
37-
output resp_t slv_resp_o,
36+
input axi_req_t slv_req_i,
37+
output axi_resp_t slv_resp_o,
3838
// master port
39-
output req_t mst_req_o,
40-
input resp_t mst_resp_i
39+
output axi_req_t mst_req_o,
40+
input axi_resp_t mst_resp_i
4141
);
4242
// AW
4343
stream_delay #(
@@ -152,11 +152,11 @@ module axi_delayer_intf #(
152152
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
153153
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
154154
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
155-
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
156-
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
155+
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
156+
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
157157

158-
req_t slv_req, mst_req;
159-
resp_t slv_resp, mst_resp;
158+
axi_req_t slv_req, mst_req;
159+
axi_resp_t slv_resp, mst_resp;
160160

161161
`AXI_ASSIGN_TO_REQ(slv_req, slv)
162162
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
@@ -170,8 +170,8 @@ module axi_delayer_intf #(
170170
.b_chan_t ( b_chan_t ),
171171
.ar_chan_t ( ar_chan_t ),
172172
.r_chan_t ( r_chan_t ),
173-
.req_t ( req_t ),
174-
.resp_t ( resp_t ),
173+
.axi_req_t ( axi_req_t ),
174+
.axi_resp_t ( axi_resp_t ),
175175
.StallRandomInput ( STALL_RANDOM_INPUT ),
176176
.StallRandomOutput ( STALL_RANDOM_OUTPUT ),
177177
.FixedDelayInput ( FIXED_DELAY_INPUT ),

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