Skip to content

Commit 9816a5b

Browse files
committed
Changelog: Add v0.19.0
1 parent 64dd7f8 commit 9816a5b

File tree

1 file changed

+7
-2
lines changed

1 file changed

+7
-2
lines changed

CHANGELOG.md

+7-2
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
99

1010
### Added
1111

12+
### Changed
13+
14+
### Fixed
15+
16+
17+
## 0.19.0 - 2020-04-21
18+
1219
### Changed
1320
- `axi_lite_to_axi`: Expose `AxCACHE` signals. It is now possible to define the `cache` signal of
1421
AXI transactions coming out of this module by driving the added `slv_aw_cache_i` and
1522
`slv_ar_cache_i` inputs. To retain the behavior prior to this change, tie those two inputs to
1623
zero.
1724

18-
### Fixed
19-
2025

2126
## 0.18.1 - 2020-04-08
2227

0 commit comments

Comments
 (0)