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axi_id_prepend: Fix single-bit case
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2 files changed

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CHANGELOG.md

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@@ -17,7 +17,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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has a single bit, and both values were correctly handled in synthesis. However, when starting
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simulation, the signal has an undefined value, and ModelSim threw warnings that this violated the
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`unique` condition.
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- `axi_id_prepend`: Fix text of some assertion messages.
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- `axi_id_prepend`:
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- Fix text of some assertion messages.
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- Fix case of prepending a single-bit ID.
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- `tb_axi_xbar`: Fix for localparam `AxiIdWidthSlaves` to be dependent on the number of masters.
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src/axi_id_prepend.sv

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@@ -76,17 +76,22 @@ module axi_id_prepend #(
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);
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// prepend the ID
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always_comb begin
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for (int unsigned i = 0; i < NoBus; i++) begin : gen_id_prepend
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mst_aw_chans_o[i] = slv_aw_chans_i[i];
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mst_aw_chans_o[i].id[AxiIdWidthSlvPort+:PreIdWidth] = pre_id_i;
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mst_ar_chans_o[i] = slv_ar_chans_i[i];
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mst_ar_chans_o[i].id[AxiIdWidthSlvPort+:PreIdWidth] = pre_id_i;
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// The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID
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// to a channel with a shorter ID correctly cuts the prepended ID.
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slv_b_chans_o[i] = mst_b_chans_i[i];
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slv_r_chans_o[i] = mst_r_chans_i[i];
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for (genvar i = 0; i < NoBus; i++) begin : gen_id_prepend
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if (PreIdWidth == 0) begin : gen_no_prepend
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assign mst_aw_chans_o[i] = slv_aw_chans_i[i];
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assign mst_ar_chans_o[i] = slv_ar_chans_i[i];
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end else begin : gen_prepend
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always_comb begin
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mst_aw_chans_o[i] = slv_aw_chans_i[i];
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mst_ar_chans_o[i] = slv_ar_chans_i[i];
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mst_aw_chans_o[i].id = {pre_id_i, slv_aw_chans_i[i].id[AxiIdWidthSlvPort-1:0]};
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mst_ar_chans_o[i].id = {pre_id_i, slv_ar_chans_i[i].id[AxiIdWidthSlvPort-1:0]};
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end
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end
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// The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID
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// to a channel with a shorter ID correctly cuts the prepended ID.
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assign slv_b_chans_o[i] = mst_b_chans_i[i];
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assign slv_r_chans_o[i] = mst_r_chans_i[i];
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end
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// assign the handshaking's and w channel

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