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Merge pull request #6 from pulp-platform/release-0.5
Release 0.5
2 parents 4989c1c + e4f831e commit d94d601

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-85
lines changed

‎Bender.yml

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@@ -3,7 +3,10 @@ package:
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authors: ["Fabian Schuiki <[email protected]>"]
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dependencies:
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common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.7.5 }
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common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.10.0 }
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export_include_dirs:
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- include
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sources:
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- src/axi_pkg.sv
@@ -12,6 +15,9 @@ sources:
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- src/axi_test.sv
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- test/tb_axi_id_remap.sv
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- test/tb_axi_delayer.sv
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- test/tb_axi_lite_to_axi.sv
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- test/tb_axi_lite_xbar.sv
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- test/tb_axi_to_axi_lite.sv
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- src/axi_intf.sv
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- src/axi_arbiter.sv

‎CHANGELOG.md

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@@ -4,12 +4,17 @@ All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
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and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
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## Unreleased
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## 0.5.0 - 2018-12-18
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- Add axi channel delayer
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### Changed
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- Remove clock from `AXI_BUS` and `AXI_LITE`. Such a clock signal is useful for testing purposes
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but confusing (or even harmful) in hardware designs. For testing purposes, the `AXI_BUS_DV` and
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`AXI_LITE_DV` (suffix for "design verification") interfaces have been defined instead.
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### Fixed
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- Update `src_files.yml` to match `Bender.yml`.
12-
- Make `axi_multicut` compatible with current definition of `AXI_BUS`.
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- Add missing `axi_test` to compile script.
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## 0.4.5 - 2018-09-12
1520
### Fixed

‎include/axi/assign.svh

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@@ -0,0 +1,90 @@
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// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
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//
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
11+
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`ifndef AXI_ASSIGN_SVH_
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`define AXI_ASSIGN_SVH_
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// Assign an AXI4 master interface to a slave interface, as in `assign slv = mst;`.
16+
`define AXI_ASSIGN(slv, mst) \
17+
assign slv.aw_id = mst.aw_id; \
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assign slv.aw_addr = mst.aw_addr; \
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assign slv.aw_len = mst.aw_len; \
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assign slv.aw_size = mst.aw_size; \
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assign slv.aw_burst = mst.aw_burst; \
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assign slv.aw_lock = mst.aw_lock; \
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assign slv.aw_cache = mst.aw_cache; \
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assign slv.aw_prot = mst.aw_prot; \
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assign slv.aw_qos = mst.aw_qos; \
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assign slv.aw_region = mst.aw_region; \
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assign slv.aw_user = mst.aw_user; \
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assign slv.aw_valid = mst.aw_valid; \
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assign mst.aw_ready = slv.aw_ready; \
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\
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assign slv.w_data = mst.w_data; \
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assign slv.w_strb = mst.w_strb; \
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assign slv.w_last = mst.w_last; \
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assign slv.w_user = mst.w_user; \
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assign slv.w_valid = mst.w_valid; \
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assign mst.w_ready = slv.w_ready; \
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\
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assign mst.b_id = slv.b_id; \
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assign mst.b_resp = slv.b_resp; \
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assign mst.b_user = slv.b_user; \
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assign mst.b_valid = slv.b_valid; \
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assign slv.b_ready = mst.b_ready; \
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\
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assign slv.ar_id = mst.ar_id; \
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assign slv.ar_addr = mst.ar_addr; \
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assign slv.ar_len = mst.ar_len; \
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assign slv.ar_size = mst.ar_size; \
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assign slv.ar_burst = mst.ar_burst; \
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assign slv.ar_lock = mst.ar_lock; \
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assign slv.ar_cache = mst.ar_cache; \
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assign slv.ar_prot = mst.ar_prot; \
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assign slv.ar_qos = mst.ar_qos; \
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assign slv.ar_region = mst.ar_region; \
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assign slv.ar_user = mst.ar_user; \
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assign slv.ar_valid = mst.ar_valid; \
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assign mst.ar_ready = slv.ar_ready; \
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\
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assign mst.r_id = slv.r_id; \
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assign mst.r_data = slv.r_data; \
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assign mst.r_resp = slv.r_resp; \
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assign mst.r_last = slv.r_last; \
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assign mst.r_user = slv.r_user; \
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assign mst.r_valid = slv.r_valid; \
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assign slv.r_ready = mst.r_ready
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// Assign an AXI4-Lite master interface to a slave interface, as in `assign slv = mst;`.
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`define AXI_LITE_ASSIGN(slv, mst) \
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assign slv.aw_addr = mst.aw_addr; \
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assign slv.aw_valid = mst.aw_valid; \
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assign mst.aw_ready = slv.aw_ready; \
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\
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assign slv.w_data = mst.w_data; \
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assign slv.w_strb = mst.w_strb; \
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assign slv.w_valid = mst.w_valid; \
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assign mst.w_ready = slv.w_ready; \
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\
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assign mst.b_resp = slv.b_resp; \
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assign mst.b_valid = slv.b_valid; \
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assign slv.b_ready = mst.b_ready; \
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\
81+
assign slv.ar_addr = mst.ar_addr; \
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assign slv.ar_valid = mst.ar_valid; \
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assign mst.ar_ready = slv.ar_ready; \
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\
85+
assign mst.r_data = slv.r_data; \
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assign mst.r_resp = slv.r_resp; \
87+
assign mst.r_valid = slv.r_valid; \
88+
assign slv.r_ready = mst.r_ready
89+
90+
`endif

‎scripts/compile_vsim.sh

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@@ -13,22 +13,5 @@
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# Fabian Schuiki <[email protected]>
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set -e
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ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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18-
[ ! -z "$VLOG" ] || VLOG=vlog
19-
[ ! -z "$VOPT" ] || VOPT=vopt
20-
21-
$VLOG -sv \
22-
"$ROOT"/src/axi_pkg.sv \
23-
"$ROOT"/src/axi_intf.sv \
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"$ROOT"/src/axi_to_axi_lite.sv \
25-
"$ROOT"/src/axi_lite_to_axi.sv \
26-
"$ROOT"/src/axi_lite_xbar.sv \
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"$ROOT"/src/axi_arbiter.sv \
28-
"$ROOT"/src/axi_address_resolver.sv \
29-
"$ROOT"/test/tb_axi_lite_to_axi.sv \
30-
"$ROOT"/test/tb_axi_to_axi_lite.sv \
31-
"$ROOT"/test/tb_axi_lite_xbar.sv \
32-
"$ROOT"/test/synth_bench.sv
33-
34-
VOPTFLAGS="+cover=bcfst+/dut"
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bender vsim -t test

‎scripts/run_vsim.sh

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@@ -22,10 +22,10 @@ call_vsim() {
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grep "Errors: 0," vsim.log
2323
}
2424

25-
# for DW in 8 16 32 64 128 256 512 1024; do
26-
# call_vsim tb_axi_lite_to_axi -GDW=$DW -t 1ps -c
27-
# call_vsim tb_axi_to_axi_lite -GDW=$DW -t 1ps -c
28-
# done
25+
for DW in 8 16 32 64 128 256 512 1024; do
26+
call_vsim tb_axi_lite_to_axi -GDW=$DW -t 1ps -c
27+
call_vsim tb_axi_to_axi_lite -GDW=$DW -t 1ps -c
28+
done
2929

3030
test_axi_lite_xbar() {
3131
call_vsim tb_axi_lite_xbar -GNUM_MASTER=$1 -GNUM_SLAVE=$2 -t 1ps -c
@@ -42,3 +42,6 @@ done
4242
for NS in 1 2 3 4 8; do
4343
test_axi_lite_xbar 4 $NS
4444
done
45+
46+
call_vsim tb_axi_delayer
47+
call_vsim tb_axi_id_remap

‎src/axi_delayer.sv

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@@ -67,11 +67,11 @@ module axi_delayer #(
6767
output logic r_ready_o
6868
);
6969
// AW
70-
ready_valid_delay #(
70+
stream_delay #(
7171
.StallRandom ( StallRandomInput ),
7272
.FixedDelay ( FixedDelayInput ),
7373
.payload_t ( aw_t )
74-
) i_ready_valid_delay_aw (
74+
) i_stream_delay_aw (
7575
.clk_i ( clk_i ),
7676
.rst_ni ( rst_ni ),
7777
.payload_i ( aw_chan_i ),
@@ -83,11 +83,11 @@ module axi_delayer #(
8383
);
8484

8585
// AR
86-
ready_valid_delay #(
86+
stream_delay #(
8787
.StallRandom ( StallRandomInput ),
8888
.FixedDelay ( FixedDelayInput ),
8989
.payload_t ( ar_t )
90-
) i_ready_valid_delay_ar (
90+
) i_stream_delay_ar (
9191
.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
9393
.payload_i ( ar_chan_i ),
@@ -99,11 +99,11 @@ module axi_delayer #(
9999
);
100100

101101
// W
102-
ready_valid_delay #(
102+
stream_delay #(
103103
.StallRandom ( StallRandomInput ),
104104
.FixedDelay ( FixedDelayInput ),
105105
.payload_t ( w_t )
106-
) i_ready_valid_delay_w (
106+
) i_stream_delay_w (
107107
.clk_i ( clk_i ),
108108
.rst_ni ( rst_ni ),
109109
.payload_i ( w_chan_i ),
@@ -115,11 +115,11 @@ module axi_delayer #(
115115
);
116116

117117
// B
118-
ready_valid_delay #(
118+
stream_delay #(
119119
.StallRandom ( StallRandomOutput ),
120120
.FixedDelay ( FixedDelayOutput ),
121121
.payload_t ( b_t )
122-
) i_ready_valid_delay_b (
122+
) i_stream_delay_b (
123123
.clk_i ( clk_i ),
124124
.rst_ni ( rst_ni ),
125125
.payload_i ( b_chan_i ),
@@ -131,11 +131,11 @@ module axi_delayer #(
131131
);
132132

133133
// R
134-
ready_valid_delay #(
134+
stream_delay #(
135135
.StallRandom ( StallRandomOutput ),
136136
.FixedDelay ( FixedDelayOutput ),
137137
.payload_t ( r_t )
138-
) i_ready_valid_delay_r (
138+
) i_stream_delay_r (
139139
.clk_i ( clk_i ),
140140
.rst_ni ( rst_ni ),
141141
.payload_i ( r_chan_i ),

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