axi_isolate: Add parameter TerminateTransaction

This parameter allows to respond to transactions during isolation.

Adapted from `0011-axi-Improve-isolation-with-termination.patch` from the
Snitch repository.

Co-authored-by: Florian Zaruba <[email protected]>

Author: andreaskurth

CHANGELOG.md

@@ -11,13 +11,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - `axi_demux`: Add parameter `AtopSupport` to optionally disable the support for atomic operations
   (ATOPs).  This parameter defaults to `1'b1`, i.e., ATOPs are supported.  Therefore, this change is
   backward-compatible.
+- `axi_isolate`: Add parameter `TerminateTransaction` to optionally respond to transactions during
+  isolation.  This parameter defaults to `1'b0`, i.e., transactions do not get responses.
+  Therefore, this change is backward-compatible.
 - `axi_xbar`: Add `Connectivity` parameter to enable the implementation of partially-connected
   crossbars.  This parameter defaults to `'1`, i.e., every slave port is connected to every master
   port.  Therefore, this change is backward-compatible.
 - `axi_test`: Add monitor class `axi_monitor`.
 - `axi_test::axi_driver`: Add monitor tasks.
 
 ### Changed
+- `axi_isolate`: Add parameters for the address, data, ID, and user signal width.  This is required
+  for the implementation of the `TerminateTransaction` parameter (see *Added* section).  This change
+  is **backward-incompatible** for all instances of `axi_isolate` outside this repository.  Users
+  must update all instances of `axi_isolate` in their code.  The interface variant is not affected
+  and remains backward-compatible.
 
 ### Fixed
 

src/axi_isolate.sv

@@ -13,6 +13,7 @@
 // - Wolfgang Roenninger <[email protected]>
 // - Andreas Kurth <[email protected]>
 
+`include "axi/typedef.svh"
 `include "common_cells/registers.svh"
 
 /// This module can isolate the AXI4+ATOPs bus on the master port from the slave port.  When the
@@ -27,9 +28,29 @@
 /// anymore, the `isolated_o` output is asserted.  As long as `isolated_o` is asserted, all output
 /// signals in `mst_req_o` are silenced to `'0`.  When isolated, new transactions initiated on the
 /// slave port are stalled until the isolation is terminated by deasserting `isolate_i`.
+///
+/// ## Response
+///
+/// If the `TerminateTransaction` parameter is set to `1'b1`, the module will return response errors
+/// in case there is an incoming transaction while the module isolates.  The data returned on the
+/// bus is `1501A7ED` (hexspeak for isolated).
+///
+/// If `TerminateTransaction` is set to `1'b0`, the transaction will block indefinitely until the
+/// module is de-isolated again.
 module axi_isolate #(
   /// Maximum number of pending requests per channel
   parameter int unsigned NumPending = 32'd16,
+  /// Gracefully terminate all incoming transactions in case of isolation by returning proper error
+  /// responses.
+  parameter bit TerminateTransaction = 1'b0,
+  /// Address width of all AXI4+ATOP ports
+  parameter int unsigned AxiAddrWidth = 32'd0,
+  /// Data width of all AXI4+ATOP ports
+  parameter int unsigned AxiDataWidth = 32'd0,
+  /// ID width of all AXI4+ATOP ports
+  parameter int unsigned AxiIdWidth = 32'd0,
+  /// User signal width of all AXI4+ATOP ports
+  parameter int unsigned AxiUserWidth = 32'd0,
   /// Request struct type of all AXI4+ATOP ports
   parameter type         axi_req_t  = logic,
   /// Response struct type of all AXI4+ATOP ports
@@ -52,6 +73,107 @@ module axi_isolate #(
   /// Master port is isolated from slave port
   output logic      isolated_o
 );
+
+  typedef logic [AxiIdWidth-1:0]     id_t;
+  typedef logic [AxiAddrWidth-1:0]   addr_t;
+  typedef logic [AxiDataWidth-1:0]   data_t;
+  typedef logic [AxiDataWidth/8-1:0] strb_t;
+  typedef logic [AxiUserWidth-1:0]   user_t;
+
+  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
+  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
+  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
+
+  axi_req_t [1:0]   demux_req;
+  axi_resp_t [1:0]  demux_rsp;
+
+  if (TerminateTransaction) begin
+    axi_demux #(
+      .AxiIdWidth     ( AxiIdWidth  ),
+      .AtopSupport    ( 1'b1        ),
+      .aw_chan_t      ( aw_chan_t   ),
+      .w_chan_t       ( w_chan_t    ),
+      .b_chan_t       ( b_chan_t    ),
+      .ar_chan_t      ( ar_chan_t   ),
+      .r_chan_t       ( r_chan_t    ),
+      .axi_req_t      ( axi_req_t   ),
+      .axi_resp_t     ( axi_resp_t  ),
+      .NoMstPorts     ( 2           ),
+      .MaxTrans       ( NumPending  ),
+      // We don't need many bits here as the common case will be to go for the pass-through.
+      .AxiLookBits    ( 1           ),
+      .UniqueIds      ( 1'b0        ),
+      .FallThrough    ( 1'b1        ),
+      .SpillAw        ( 1'b0        ),
+      .SpillW         ( 1'b0        ),
+      .SpillB         ( 1'b0        ),
+      .SpillAr        ( 1'b0        ),
+      .SpillR         ( 1'b0        )
+    ) i_axi_demux (
+      .clk_i,
+      .rst_ni,
+      .test_i          ( 1'b0       ),
+      .slv_req_i,
+      .slv_aw_select_i ( isolated_o ),
+      .slv_ar_select_i ( isolated_o ),
+      .slv_resp_o,
+      .mst_reqs_o      ( demux_req ),
+      .mst_resps_i     ( demux_rsp )
+    );
+
+    axi_err_slv #(
+      .AxiIdWidth  ( AxiIdWidth           ),
+      .axi_req_t   ( axi_req_t            ),
+      .axi_resp_t  ( axi_resp_t           ),
+      .Resp        ( axi_pkg::RESP_DECERR ),
+      .RespData    ( 'h1501A7ED           ),
+      .ATOPs       ( 1'b1                 ),
+      .MaxTrans    ( 1                    )
+    ) i_axi_err_slv (
+      .clk_i,
+      .rst_ni,
+      .test_i     ( 1'b0         ),
+      .slv_req_i  ( demux_req[1] ),
+      .slv_resp_o ( demux_rsp[1] )
+    );
+  end else begin
+    assign demux_req[0] = slv_req_i;
+    assign slv_resp_o = demux_rsp[0];
+  end
+
+  axi_isolate_inner #(
+    .NumPending ( NumPending  ),
+    .axi_req_t  ( axi_req_t   ),
+    .axi_resp_t ( axi_resp_t  )
+  ) i_axi_isolate (
+    .clk_i,
+    .rst_ni,
+    .slv_req_i  ( demux_req[0] ),
+    .slv_resp_o ( demux_rsp[0] ),
+    .mst_req_o,
+    .mst_resp_i,
+    .isolate_i,
+    .isolated_o
+  );
+endmodule
+
+module axi_isolate_inner #(
+  parameter int unsigned NumPending = 32'd16,
+  parameter type         axi_req_t  = logic,
+  parameter type         axi_resp_t = logic
+) (
+  input  logic      clk_i,
+  input  logic      rst_ni,
+  input  axi_req_t  slv_req_i,
+  output axi_resp_t slv_resp_o,
+  output axi_req_t  mst_req_o,
+  input  axi_resp_t mst_resp_i,
+  input  logic      isolate_i,
+  output logic      isolated_o
+);
+
   // plus 1 in clog for accouning no open transaction, plus one bit for atomic injection
   localparam int unsigned CounterWidth = $clog2(NumPending + 32'd1) + 32'd1;
   typedef logic [CounterWidth-1:0] cnt_t;
@@ -283,14 +405,14 @@ module axi_isolate #(
 // pragma translate_on
 endmodule
 
-`include "axi/typedef.svh"
 `include "axi/assign.svh"
 
 /// Interface variant of [`axi_isolate`](module.axi_isolate).
 ///
 /// See the documentation of the main module for the definition of ports and parameters.
 module axi_isolate_intf #(
   parameter int unsigned NUM_PENDING    = 32'd16,
+  parameter bit TERMINATE_TRANSACTION   = 1'b0,
   parameter int unsigned AXI_ID_WIDTH   = 32'd0,
   parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
   parameter int unsigned AXI_DATA_WIDTH = 32'd0,
@@ -329,9 +451,14 @@ module axi_isolate_intf #(
   `AXI_ASSIGN_TO_RESP(mst_resp, mst)
 
   axi_isolate #(
-    .NumPending ( NUM_PENDING ),
-    .axi_req_t  ( axi_req_t   ),
-    .axi_resp_t ( axi_resp_t  )
+    .NumPending           ( NUM_PENDING           ),
+    .TerminateTransaction ( TERMINATE_TRANSACTION ),
+    .AxiAddrWidth         ( AXI_ADDR_WIDTH        ),
+    .AxiDataWidth         ( AXI_DATA_WIDTH        ),
+    .AxiIdWidth           ( AXI_ID_WIDTH          ),
+    .AxiUserWidth         ( AXI_USER_WIDTH        ),
+    .axi_req_t            ( axi_req_t             ),
+    .axi_resp_t           ( axi_resp_t            )
   ) i_axi_isolate (
     .clk_i,
     .rst_ni,