@@ -24,15 +24,15 @@ module axi_to_detailed_mem #(
24
24
// / Address width, has to be less or equal than the width off the AXI address field.
25
25
// / Determines the width of `mem_addr_o`. Has to be wide enough to emit the memory region
26
26
// / which should be accessible.
27
- parameter int unsigned AddrWidth = 0 ,
27
+ parameter int unsigned AddrWidth = 1 ,
28
28
// / AXI4+ATOP data width.
29
- parameter int unsigned DataWidth = 0 ,
29
+ parameter int unsigned DataWidth = 1 ,
30
30
// / AXI4+ATOP ID width.
31
- parameter int unsigned IdWidth = 0 ,
31
+ parameter int unsigned IdWidth = 1 ,
32
32
// / AXI4+ATOP user width.
33
- parameter int unsigned UserWidth = 0 ,
33
+ parameter int unsigned UserWidth = 1 ,
34
34
// / Number of banks at output, must evenly divide `DataWidth`.
35
- parameter int unsigned NumBanks = 0 ,
35
+ parameter int unsigned NumBanks = 1 ,
36
36
// / Depth of memory response buffer. This should be equal to the memory response latency.
37
37
parameter int unsigned BufDepth = 1 ,
38
38
// / Hide write requests if the strb == '0
0 commit comments