Made aux chain modules lane-agnostic.

Author: Maurus Item

src/fpnew_aux.sv

@@ -21,32 +21,25 @@
 module fpnew_aux #(
   parameter int unsigned             NumPipeRegs = 0,
   parameter type                     TagType     = logic,
-  parameter type                     AuxType     = logic,
-  parameter int unsigned             NumLanes    = 1
+  parameter type                     AuxType     = logic
 ) (
   input logic                                  clk_i,
   input logic                                  rst_ni,
   // Input signals
   input TagType                                tag_i,
   input AuxType                                aux_i,
-  input logic                                  is_vector_i,
-  input logic [NumLanes-1:0]                   lane_active_i,        
   // Input Handshake
   input  logic                                 in_valid_i,
   output logic                                 in_ready_o,
   input  logic                                 flush_i,
   // Output signals
   output TagType                               tag_o,
   output AuxType                               aux_o,
-  output logic                                 is_vector_o,
-  output logic [NumLanes-1:0]                  lane_active_o,        
   // Output handshake
   output logic                                 out_valid_o,
   input  logic                                 out_ready_i,
   // Register Enable for Lanes
   output logic [NumPipeRegs-1:0]               reg_enable_o,
-  output logic [NumPipeRegs-1:0]               vector_reg_enable_o,
-  output logic [NumLanes-1:0][NumPipeRegs-1:0] lane_reg_enable_o,
   // Indication of valid data in flight
   output logic                                 busy_o
 );
@@ -58,8 +51,6 @@ module fpnew_aux #(
   // Input pipeline signals, index i holds signal after i register stages
   TagType                [0:NumPipeRegs]                 tag;
   AuxType                [0:NumPipeRegs]                 aux;
-  logic                  [0:NumPipeRegs]                 is_vector;
-  logic                  [0:NumPipeRegs][NumLanes-1:0]   lane_active;
   logic                  [0:NumPipeRegs]                 valid;
 
   // Ready signal is combinatorial for all stages
@@ -68,9 +59,7 @@ module fpnew_aux #(
   // First element of pipeline is taken from inputs
   assign tag        [0] = tag_i;
   assign aux        [0] = aux_i;
-  assign is_vector  [0] = is_vector_i;
   assign valid      [0] = in_valid_i;
-  assign lane_active[0] = lane_active_i;
 
   // Propagate pipeline ready signal to upstream circuitry
   assign in_ready_o = ready[0];
@@ -88,23 +77,12 @@ module fpnew_aux #(
     // Valid: enabled by ready signal, synchronous clear with the flush signal
     `FFLARNC(valid[i+1], valid[i], ready[i], flush_i, 1'b0, clk_i, rst_ni)
 
-    // Enable register if pipleine ready and a valid data item is present
-    assign reg_ena = ready[i] & valid[i];
-
-    // Drive external registers with reg enable
-    assign reg_enable_o[i] = reg_ena;
-
-    // Drive external vector registers with reg enable if operation is a vector
-    assign vector_reg_enable_o[i] = reg_ena & is_vector[i];
-    for (genvar l = 0; l < NumLanes; l++) begin
-      assign lane_reg_enable_o[l][i] = reg_ena & lane_active[i][l];
-    end
+    // Enable register if pipeline ready and a valid data item is present
+    assign reg_enable_o[i] = ready[i] & valid[i];
 
     // Generate the pipeline registers within the stages, use enable-registers
-    `FFL(        tag[i+1],         tag[i], reg_ena, TagType'('0))
-    `FFL(        aux[i+1],         aux[i], reg_ena, AuxType'('0))
-    `FFL(  is_vector[i+1],   is_vector[i], reg_ena, '0          )
-    `FFL(lane_active[i+1], lane_active[i], reg_ena, '0          )
+    `FFL(        tag[i+1],         tag[i], reg_enable_o[i], TagType'('0))
+    `FFL(        aux[i+1],         aux[i], reg_enable_o[i], AuxType'('0))
   end
 
   // Ready travels backwards from output side, driven by downstream circuitry
@@ -113,9 +91,7 @@ module fpnew_aux #(
   // Assign module outputs
   assign tag_o           = tag        [NumPipeRegs];
   assign aux_o           = aux        [NumPipeRegs];
-  assign is_vector_o     = is_vector  [NumPipeRegs];
   assign out_valid_o     = valid      [NumPipeRegs];
-  assign lane_active_o   = lane_active[NumPipeRegs];
 
   // Assign output Flags: Busy if any element inside the pipe is valid
   assign busy_o          = |valid;

src/fpnew_aux_fsm.sv

@@ -23,37 +23,28 @@ module fpnew_aux_fsm #(
   parameter int unsigned             NumPipeRegs = 0,
   parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::BEFORE,
   parameter type                     TagType     = logic,
-  parameter type                     AuxType     = logic,
-  parameter int unsigned             NumLanes    = 1
+  parameter type                     AuxType     = logic
 ) (
   input logic                                  clk_i,
   input logic                                  rst_ni,
   // Input signals
   input TagType                                tag_i,
   input AuxType                                aux_i,
-  input logic                                  is_vector_i,
-  input logic [NumLanes-1:0]                   lane_active_i,        
   // Input Handshake
   input  logic                                 in_valid_i,
   output logic                                 in_ready_o,
   input  logic                                 flush_i,
   // Output signals
   output TagType                               tag_o,
   output AuxType                               aux_o,
-  output logic                                 is_vector_o,
-  output logic [NumLanes-1:0]                  lane_active_o,        
   // Output handshake
   output logic                                 out_valid_o,
   input  logic                                 out_ready_i,
   // Register Enable for Lanes
   output logic [NumPipeRegs-1:0]               reg_enable_o,
-  output logic [NumPipeRegs-1:0]               vector_reg_enable_o,
-  output logic [NumLanes-1:0][NumPipeRegs-1:0] lane_reg_enable_o,
   // Signals for the Lane FSMs
-  // Signal to start the FSM, will be asserted for one cycle
-  output logic [NumLanes-1:0]                  lane_fsm_start_o,
-  // Signal that the FSM finished it's operation, should be asserted continuously
-  input logic [NumLanes-1:0]                   lane_fsm_ready_i,
+  output logic                                 fsm_start_o,
+  input logic                                  fsm_ready_i,
   // Indication of valid data in flight
   output logic                                 busy_o
 );
@@ -79,8 +70,6 @@ module fpnew_aux_fsm #(
   // Input pipeline signals, index i holds signal after i register stages
   TagType [0:NUM_INP_REGS]               in_tag;
   AuxType [0:NUM_INP_REGS]               in_aux;
-  logic   [0:NUM_INP_REGS]               in_is_vector;
-  logic   [0:NUM_INP_REGS][NumLanes-1:0] in_lane_active;
   logic   [0:NUM_INP_REGS]               in_valid;
 
   // Ready signal is combinatorial for all stages
@@ -89,16 +78,14 @@ module fpnew_aux_fsm #(
   // First element of pipeline is taken from inputs
   assign in_tag        [0] = tag_i;
   assign in_aux        [0] = aux_i;
-  assign in_is_vector  [0] = is_vector_i;
   assign in_valid      [0] = in_valid_i;
-  assign in_lane_active[0] = lane_active_i;
 
   // Propagate pipeline ready signal to upstream circuitry
   assign in_ready_o = in_ready[0];
 
   // Generate the register stages
   for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline
-
+    
     // Internal register enable for this stage
     logic reg_ena;
     // Determine the ready signal of the current stage - advance the pipeline:
@@ -110,22 +97,11 @@ module fpnew_aux_fsm #(
     `FFLARNC(in_valid[i+1], in_valid[i], in_ready[i], flush_i, 1'b0, clk_i, rst_ni)
 
     // Enable register if pipleine ready and a valid data item is present
-    assign reg_ena = in_ready[i] & in_valid[i];
-
-    // Drive external registers with reg enable
-    assign reg_enable_o[i] = reg_ena;
-
-    // Drive external vector registers with reg enable if operation is a vector
-    assign vector_reg_enable_o[i] = reg_ena & in_is_vector[i];
-    for (genvar l = 0; l < NumLanes; l++) begin
-      assign lane_reg_enable_o[l][i] = reg_ena & in_lane_active[i][l];
-    end
+    assign reg_enable_o[i] = in_ready[i] & in_valid[i];
 
     // Generate the pipeline registers within the stages, use enable-registers
-    `FFL(        in_tag[i+1],         in_tag[i], reg_ena, TagType'('0))
-    `FFL(        in_aux[i+1],         in_aux[i], reg_ena, AuxType'('0))
-    `FFL(  in_is_vector[i+1],   in_is_vector[i], reg_ena, '0          )
-    `FFL(in_lane_active[i+1], in_lane_active[i], reg_ena, '0          )
+    `FFL(        in_tag[i+1],         in_tag[i], reg_enable_o[i], TagType'('0))
+    `FFL(        in_aux[i+1],         in_aux[i], reg_enable_o[i], AuxType'('0))
   end
 
   // ----------
@@ -140,28 +116,22 @@ module fpnew_aux_fsm #(
   logic fsm_in_valid, fsm_in_ready;
   logic fsm_out_valid, fsm_out_ready;
 
-  // Synchronisazion signals
-  logic fsm_start, fsm_ready, fsm_busy;
+  logic fsm_busy;
 
   // Data holding signals
   TagType                held_tag;
   AuxType                held_aux;
-  logic                  held_is_vector;
-  logic   [NumLanes-1:0] held_lane_active;
 
   // Upstream Handshake Connection
   assign fsm_in_valid = in_valid[NUM_INP_REGS];
   assign in_ready[NUM_INP_REGS] = fsm_in_ready;
 
-  // Done when all active lanes are done
-  assign fsm_ready = &lane_fsm_ready_i;
-
   // FSM to safely apply and receive data from DIVSQRT unit
   always_comb begin : flag_fsm
     // Default assignments
     fsm_out_valid = 1'b0;
     fsm_in_ready  = 1'b0;
-    fsm_start     = 1'b0;
+    fsm_start_o   = 1'b0;
     fsm_busy      = 1'b0;
     state_d       = state_q;
 
@@ -170,19 +140,19 @@ module fpnew_aux_fsm #(
         fsm_in_ready = '1;
         if (fsm_in_valid) begin
           state_d = BUSY;
-          fsm_start = 1'b1;
+          fsm_start_o = 1'b1;
         end
       end
       BUSY: begin
         fsm_busy = 1'b1;
         // If all active lanes are done send data down chain
-        if (fsm_ready) begin
+        if (fsm_ready_i) begin
           fsm_out_valid = 1'b1;
           if (fsm_out_ready) begin
             fsm_in_ready = 1'b1;
             if (fsm_in_valid) begin
               state_d = BUSY;
-              fsm_start = 1'b1;
+              fsm_start_o = 1'b1;
             end else begin
               state_d = IDLE;
             end
@@ -198,7 +168,7 @@ module fpnew_aux_fsm #(
           fsm_in_ready = 1'b1;
           if (fsm_in_valid) begin
             state_d = BUSY;
-            fsm_start = 1'b1;
+            fsm_start_o = 1'b1;
           end else begin
             state_d = IDLE;
           end
@@ -220,19 +190,12 @@ module fpnew_aux_fsm #(
 
   `FF(state_q, state_d, IDLE);
 
-  // Start Lanes when FSM starts and lane is active
-  for (genvar l = 0; l < NumLanes; l++) begin
-    assign lane_fsm_start_o[l] = fsm_start && in_lane_active[NUM_INP_REGS][l];
-  end
-
   // ----------------
   // Data Holding FFs
   // ----------------
 
-  `FFL(        held_tag,         in_tag[NUM_INP_REGS], fsm_start, TagType'('0));
-  `FFL(        held_aux,         in_aux[NUM_INP_REGS], fsm_start, AuxType'('0));
-  `FFL(  held_is_vector,   in_is_vector[NUM_INP_REGS], fsm_start,           '0);
-  `FFL(held_lane_active, in_lane_active[NUM_INP_REGS], fsm_start,           '0);
+  `FFL(        held_tag,         in_tag[NUM_INP_REGS], fsm_start_o, TagType'('0));
+  `FFL(        held_aux,         in_aux[NUM_INP_REGS], fsm_start_o, AuxType'('0));
 
   // ---------------
   // Output pipeline
@@ -241,8 +204,6 @@ module fpnew_aux_fsm #(
   // Output pipeline signals, index i holds signal after i register stages
   TagType [0:NUM_OUT_REGS]               out_tag;
   AuxType [0:NUM_OUT_REGS]               out_aux;
-  logic   [0:NUM_OUT_REGS]               out_is_vector;
-  logic   [0:NUM_OUT_REGS][NumLanes-1:0] out_lane_active;
   logic   [0:NUM_OUT_REGS]               out_valid;
 
   // Ready signal is combinatorial for all stages
@@ -255,8 +216,6 @@ module fpnew_aux_fsm #(
   // Connect to Hold Register
   assign out_tag        [0] = held_tag;
   assign out_aux        [0] = held_aux;
-  assign out_is_vector  [0] = held_is_vector;
-  assign out_lane_active[0] = held_lane_active;
 
   // Generate the register stages
   for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline
@@ -277,17 +236,9 @@ module fpnew_aux_fsm #(
     // Drive external registers with reg enable
     assign reg_enable_o[NUM_INP_REGS + i] = reg_ena;
 
-    // Drive external vector registers with reg enable if operation is a vector
-    assign vector_reg_enable_o[NUM_INP_REGS + i] = reg_ena & out_is_vector[i];
-    for (genvar l = 0; l < NumLanes; l++) begin
-      assign lane_reg_enable_o[l][NUM_INP_REGS + i] = reg_ena & out_lane_active[i][l];
-    end
-
     // Generate the pipeline registers within the stages, use enable-registers
     `FFL(        out_tag[i+1],         out_tag[i], reg_ena, TagType'('0))
     `FFL(        out_aux[i+1],         out_aux[i], reg_ena, AuxType'('0))
-    `FFL(  out_is_vector[i+1],   out_is_vector[i], reg_ena, '0          )
-    `FFL(out_lane_active[i+1], out_lane_active[i], reg_ena, '0          )
   end
 
   // Ready travels backwards from output side, driven by downstream circuitry
@@ -296,9 +247,7 @@ module fpnew_aux_fsm #(
   // Assign module outputs
   assign tag_o           = out_tag        [NUM_OUT_REGS];
   assign aux_o           = out_aux        [NUM_OUT_REGS];
-  assign is_vector_o     = out_is_vector  [NUM_OUT_REGS];
   assign out_valid_o     = out_valid      [NUM_OUT_REGS];
-  assign lane_active_o   = out_lane_active[NUM_OUT_REGS];
 
   // Assign output Flags: Busy if any element inside the pipe is valid
   assign busy_o          = |in_valid | |out_valid | fsm_busy;