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tree: Add support for multiple NoC configuration (#8)
* Remove SPM tile and generalize dummy insertion * Generalize for multile cfg * Add util to generate c-header from yml * Add mini config for backend trials * Fix sw flow
1 parent a818eb5 commit bfab993

18 files changed

Lines changed: 231 additions & 349 deletions

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.gitlab/sw-tests.yml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/multicast_benchmark.elf }
2727
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/multi_mcast.elf }
2828
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/row_col_mcast.elf }
29-
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: $SN_BUILD_DIR/access_spm.elf }
3029
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: sw/snitch/apps/gemm_2d/build/gemm_2d.elf, VERIFY_PY: $SN_ROOT/sw/kernels/blas/gemm/scripts/verify.py, PRELMODE: 3 }
3130
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: sw/snitch/apps/fused_concat_linear/build/fused_concat_linear.elf, VERIFY_PY: $SN_ROOT/sw/kernels/dnn/fused_concat_linear/scripts/verify.py, PRELMODE: 3 }
3231
- { CHS_BINARY: $CHS_BUILD_DIR/simple_offload.spm.elf, SN_BINARY: sw/snitch/apps/mha/build/mha.elf, VERIFY_PY: $SN_ROOT/sw/kernels/dnn/mha/scripts/verify.py, PRELMODE: 3 }

Bender.yml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ sources:
5050
- hw/cluster_tile.sv
5151
- hw/cheshire_tile.sv
5252
- hw/mem_tile.sv
53-
- hw/spm_tile.sv
5453
- hw/dummy_tile.sv
5554

5655
# Level 3

Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
GW_ROOT ?= $(shell pwd -P)
88
GW_GEN_DIR = $(GW_ROOT)/.generated
99
BENDER_ROOT ?= $(GW_ROOT)/.bender
10+
UTIL_DIR = $(GW_ROOT)/util
1011

1112
# Executables — must be defined before dependency paths that call $(BENDER)
1213
BENDER ?= bender --suppress W22 -d $(GW_ROOT)

cfg/gwaihir_noc.yml

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -88,18 +88,6 @@ endpoints:
8888
sbr_port_protocol:
8989
- "narrow_out"
9090
- "wide_out"
91-
- name: "top_spm_narrow"
92-
addr_range:
93-
start: 0x6000_0000
94-
size: 0x0004_0000
95-
sbr_port_protocol:
96-
- "narrow_out"
97-
- name: "top_spm_wide"
98-
addr_range:
99-
start: 0x6004_0000
100-
size: 0x0004_0000
101-
sbr_port_protocol:
102-
- "wide_out"
10391
- name: "l2_spm"
10492
array: [8]
10593
addr_range:
@@ -156,14 +144,6 @@ connections:
156144
- [0, 0]
157145
- [0, 3]
158146
dst_dir: "Eject"
159-
- src: "top_spm_narrow"
160-
dst: "router_right"
161-
dst_idx: [1, 2]
162-
dst_dir: "Eject"
163-
- src: "top_spm_wide"
164-
dst: "router_right"
165-
dst_idx: [1, 1]
166-
dst_dir: "Eject"
167147
# router_left (x=0) ↔ router_center West boundary (x=4)
168148
- src: "router_left"
169149
dst: "router_center"

cfg/mini_gwaihir_noc.yml

Lines changed: 32 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,15 @@ network_type: "narrow-wide"
99
routing:
1010
route_algo: "XY"
1111
use_id_table: true
12-
en_multicast: true
12+
collective:
13+
en_narrow_multicast: true
14+
en_wide_multicast: true
15+
en_barrier: true
16+
en_wide_reduction: # selective FP ops, default hw config
17+
rd_pipeline_depth: 5
18+
cut_offload_intf: true
19+
decouple_rw: Phys
20+
vc_impl: naive
1321

1422
protocols:
1523
- name: "narrow_in"
@@ -18,36 +26,47 @@ protocols:
1826
data_width: 64
1927
addr_width: 48
2028
id_width: 5
21-
user_width: 3
29+
user_width:
30+
collective_mask: 48
31+
collective_op: 4
32+
user: 5
2233
- name: "narrow_out"
2334
type: "narrow"
2435
protocol: "AXI4"
2536
data_width: 64
2637
addr_width: 48
2738
id_width: 2
28-
user_width: 3
39+
user_width:
40+
collective_mask: 48
41+
collective_op: 4
42+
user: 5
2943
- name: "wide_in"
3044
type: "wide"
3145
protocol: "AXI4"
3246
data_width: 512
3347
addr_width: 48
3448
id_width: 3
35-
user_width: 1
49+
user_width:
50+
collective_mask: 48
51+
collective_op: 4
3652
- name: "wide_out"
3753
type: "wide"
3854
protocol: "AXI4"
3955
data_width: 512
4056
addr_width: 48
4157
id_width: 1
42-
user_width: 1
58+
user_width:
59+
collective_mask: 48
60+
collective_op: 4
4361

4462
endpoints:
4563
- name: "cluster"
4664
array: [2, 2]
4765
addr_range:
4866
base: 0x2000_0000
4967
size: 0x0004_0000
50-
rdl_name: "snitch_tile"
68+
rdl_name: "snitch_cluster"
69+
en_collective: true
5170
mgr_port_protocol:
5271
- "narrow_in"
5372
- "wide_in"
@@ -70,7 +89,7 @@ endpoints:
7089
- "narrow_out"
7190
- "wide_out"
7291
- name: "l2_spm"
73-
array: [1]
92+
array: [2]
7493
addr_range:
7594
base: 0x7000_0000
7695
size: 0x0010_0000
@@ -80,7 +99,7 @@ endpoints:
8099

81100
routers:
82101
- name: "router"
83-
array: [3, 2]
102+
array: [4, 2]
84103
degree: 5
85104

86105
connections:
@@ -95,11 +114,13 @@ connections:
95114
dst_dir: "Eject"
96115
- src: "cheshire"
97116
dst: "router"
98-
dst_idx: [2, 0]
117+
dst_idx: [3, 1]
99118
dst_dir: "Eject"
100119
- src: "l2_spm"
101120
dst: "router"
102121
src_range:
103-
- [0, 0]
104-
dst_idx: [2, 1]
122+
- [0, 1]
123+
dst_range:
124+
- [2, 2]
125+
- [0, 1]
105126
dst_dir: "Eject"

hw/gwaihir_pkg.sv

Lines changed: 38 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -180,37 +180,53 @@ package gwaihir_pkg;
180180
// Dummy tiles X, Y coordinates
181181
typedef id_t [NumDummyTiles-1:0] dummy_idx_t;
182182

183-
// This function is used to identify
184-
function automatic dummy_idx_t get_dummy_idx(mesh_map_t MeshMap, int Dim_x, int Dim_y);
185-
dummy_idx_t dummy_idx;
186-
int unsigned empty_tile = 0;
187-
int unsigned found_tiles = 0;
183+
// For each (col, row) in MeshMap: if the column is not fully empty (has at least one
184+
// occupied tile) but this specific position is unoccupied, insert a dummy tile there.
185+
// The returned indices are in SAM-space coordinates (matching MeshMap).
186+
function automatic dummy_idx_t get_dummy_idx(mesh_map_t MeshMap);
187+
dummy_idx_t dummy_idx;
188+
int unsigned found_tiles;
189+
bit [MaxId.x:0] empty_cols;
190+
191+
found_tiles = 0;
192+
empty_cols = get_empty_cols(MeshMap);
188193

189-
// Count the number of columns that have at least one tile
190194
for (int col = 0; col <= MaxId.x; col++) begin
191-
// Clear counter for the next column
192-
empty_tile = 0;
193-
for (int row = 0; row <= MaxId.y; row++) begin
194-
if (MeshMap[row][col] == 1'b1) begin
195-
end else if (empty_tile <= MaxId.y) begin
196-
// If the tile is empty, we can add it to the dummy index
197-
dummy_idx[found_tiles] = '{x : col, y : row, port_id: 0};
198-
found_tiles++;
199-
empty_tile++;
200-
end else begin
201-
// If the full column is empty, we don't need to insert dummy tiles
202-
found_tiles -= empty_tile;
203-
break;
195+
if (!empty_cols[col]) begin
196+
for (int row = 0; row <= MaxId.y; row++) begin
197+
if (MeshMap[row][col] == 1'b0) begin
198+
dummy_idx[found_tiles] = '{x: col, y: row, port_id: 0};
199+
found_tiles++;
200+
end
204201
end
205202
end
206203
end
207204
return dummy_idx;
208205
endfunction
209206

210-
// localparam dummy_idx_t DummyIdx = get_dummy_idx(MeshMap, MeshDim.x, MeshDim.y);
211-
localparam dummy_idx_t DummyIdx = '{'{x: 9, y: 0, port_id: 0}};
212-
localparam dummy_idx_t DummyPhysicalIdx = '{'{x: 6, y: 0, port_id: 0}};
207+
// For each SAM-space dummy index, subtract the number of fully-empty columns that lie
208+
// to its left. This gives the physical array index used to connect floo_req/rsp signals,
209+
// mirroring the same transformation applied to SamPhysical via align_x_coordinate.
210+
function automatic dummy_idx_t get_dummy_physical_idx(dummy_idx_t dummy_idx);
211+
dummy_idx_t ret;
212+
int unsigned left_empty_cols;
213+
int unsigned current_x;
214+
215+
for (int d = 0; d < NumDummyTiles; d++) begin
216+
current_x = int'(dummy_idx[d].x);
217+
left_empty_cols = 0;
218+
for (int col = 0; col < current_x; col++) begin
219+
if (EmptyCols[col] == 1'b1) left_empty_cols++;
220+
end
221+
ret[d].x = dummy_idx[d].x - left_empty_cols;
222+
ret[d].y = dummy_idx[d].y;
223+
ret[d].port_id = dummy_idx[d].port_id;
224+
end
225+
return ret;
226+
endfunction
213227

228+
localparam dummy_idx_t DummyIdx = get_dummy_idx(MeshMap);
229+
localparam dummy_idx_t DummyPhysicalIdx = get_dummy_physical_idx(DummyIdx);
214230

215231
// Whether the connection is a tie-off or a valid neighbor
216232
function automatic bit is_tie_off(int x, int y, route_direction_e dir);
@@ -345,68 +361,5 @@ package gwaihir_pkg;
345361
localparam int unsigned SramAddrWidthOffset = SramBankSelOffset + SramBankSelWidth;
346362
localparam int unsigned SramMacroSelOffset = SramAddrWidthOffset + SramAddrWidth;
347363

348-
////////////////////////
349-
// SPM Narrow Tiles //
350-
////////////////////////
351-
352-
// Narrow SPM tile size
353-
localparam int unsigned SpmNarrowTileSize = ep_addr_size(TopSpmNarrowSamIdx);
354-
// Narrow SPM number words per bank
355-
localparam int unsigned SpmNarrowWordsPerBank = 2048; // in #words
356-
// Narrow SPM dataWidth
357-
localparam int unsigned SpmNarrowDataWidth = 64; // in bits
358-
359-
// Narrow SPM number of banks per word
360-
localparam int unsigned SpmNarrowNumBanksPerWord = AxiCfgN.DataWidth / SpmNarrowDataWidth;
361-
// Narrow SPM number of bank rows
362-
localparam int unsigned SpmNarrowNumBankRows = (SpmNarrowTileSize / (AxiCfgN.DataWidth / 8)
363-
/ SpmNarrowWordsPerBank);
364-
365-
// The number of LSBs to address the bytes in an SRAM word
366-
localparam int unsigned SpmNarrowByteOffsetWidth = $clog2(SpmNarrowDataWidth / 8);
367-
// The number of bits required to select the subbank for a Narrow word
368-
localparam int unsigned SpmNarrowBankSelWidth = $clog2(SpmNarrowNumBanksPerWord);
369-
// The number of bits for the SpmNarrow address
370-
localparam int unsigned SpmNarrowAddrWidth = $clog2(SpmNarrowWordsPerBank);
371-
// The number of bits to index the SpmNarrow macro
372-
localparam int unsigned SpmNarrowMacroSelWidth = $clog2(SpmNarrowNumBankRows);
373-
374-
// Various offsets for the SpmNarrow address
375-
localparam int unsigned SpmNarrowBankSelOffset = SpmNarrowByteOffsetWidth;
376-
localparam int unsigned SpmNarrowAddrWidthOffset = SpmNarrowBankSelOffset + SpmNarrowBankSelWidth;
377-
localparam int unsigned SpmNarrowMacroSelOffset = SpmNarrowAddrWidthOffset + SpmNarrowAddrWidth;
378-
379-
380-
//////////////////////
381-
// SPM Wide Tiles //
382-
//////////////////////
383-
384-
// Wide SPM tile
385-
localparam int unsigned SpmWideTileSize = ep_addr_size(TopSpmWideSamIdx);
386-
// Wide SPM number words per bank
387-
localparam int unsigned SpmWideWordsPerBank = 1024; // in #words
388-
// Wide SPM dataWidth
389-
localparam int unsigned SpmWideDataWidth = 128; // in bits
390-
391-
// Wide SPM number of banks per word
392-
localparam int unsigned SpmWideNumBanksPerWord = AxiCfgW.DataWidth / SpmWideDataWidth;
393-
// Wide SPM number of bank rows
394-
localparam int unsigned SpmWideNumBankRows = (SpmWideTileSize / (AxiCfgW.DataWidth / 8)
395-
/ SpmWideWordsPerBank);
396-
397-
// The number of LSBs to address the bytes in an SRAM word
398-
localparam int unsigned SpmWideByteOffsetWidth = $clog2(SpmWideDataWidth / 8);
399-
// The number of bits required to select the subbank for a wide word
400-
localparam int unsigned SpmWideBankSelWidth = $clog2(SpmWideNumBanksPerWord);
401-
// The number of bits for the SpmWide address
402-
localparam int unsigned SpmWideAddrWidth = $clog2(SpmWideWordsPerBank);
403-
// The number of bits to index the SpmWide macro
404-
localparam int unsigned SpmWideMacroSelWidth = $clog2(SpmWideNumBankRows);
405-
406-
// Various offsets for the SpmWide address
407-
localparam int unsigned SpmWideBankSelOffset = SpmWideByteOffsetWidth;
408-
localparam int unsigned SpmWideAddrWidthOffset = SpmWideBankSelOffset + SpmWideBankSelWidth;
409-
localparam int unsigned SpmWideMacroSelOffset = SpmWideAddrWidthOffset + SpmWideAddrWidth;
410-
411364

412365
endpackage

hw/gwaihir_top.sv

Lines changed: 0 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -233,82 +233,6 @@ module gwaihir_top
233233

234234
end
235235

236-
///////////////
237-
// SPM tile //
238-
///////////////
239-
240-
// Narrow SPM tile
241-
localparam int SpmNarrowTileSamIdx = int'(TopSpmNarrowSamIdx);
242-
localparam id_t SpmNarrowTileId = CollectiveSam[SpmNarrowTileSamIdx].idx.id;
243-
localparam id_t SpmNarrowTilePhysicalId = SamPhysical[SpmNarrowTileSamIdx].idx;
244-
localparam int SpmNarrowTileX = int'(SpmNarrowTilePhysicalId.x);
245-
localparam int SpmNarrowTileY = int'(SpmNarrowTilePhysicalId.y);
246-
247-
spm_tile #(
248-
.axi_aw_chan_t (floo_gwaihir_noc_pkg::axi_narrow_out_aw_chan_t),
249-
.axi_w_chan_t (floo_gwaihir_noc_pkg::axi_narrow_out_w_chan_t),
250-
.axi_b_chan_t (floo_gwaihir_noc_pkg::axi_narrow_out_b_chan_t),
251-
.axi_ar_chan_t (floo_gwaihir_noc_pkg::axi_narrow_out_ar_chan_t),
252-
.axi_r_chan_t (floo_gwaihir_noc_pkg::axi_narrow_out_r_chan_t),
253-
.axi_to_mem_req_t (floo_gwaihir_noc_pkg::axi_narrow_out_req_t),
254-
.axi_to_mem_rsp_t (floo_gwaihir_noc_pkg::axi_narrow_out_rsp_t),
255-
.AxiIdWidth (AxiCfgN.InIdWidth),
256-
.AxiDataWidth (AxiCfgN.DataWidth),
257-
.SpmTileSize (SpmNarrowTileSize),
258-
.SpmWordsPerBank (SpmNarrowWordsPerBank),
259-
.SpmDataWidth (SpmNarrowDataWidth),
260-
.SpmNumBanksPerWord(SpmNarrowNumBanksPerWord),
261-
.SpmNumBankRows (SpmNarrowNumBankRows),
262-
.IsNarrow (1'b1)
263-
) i_narrow_spm_tile (
264-
.clk_i,
265-
.rst_ni,
266-
.test_enable_i(test_mode_i),
267-
.id_i (SpmNarrowTileId),
268-
.floo_req_o (floo_req_out[SpmNarrowTileX][SpmNarrowTileY]),
269-
.floo_rsp_i (floo_rsp_in[SpmNarrowTileX][SpmNarrowTileY]),
270-
.floo_wide_o (floo_wide_out[SpmNarrowTileX][SpmNarrowTileY]),
271-
.floo_req_i (floo_req_in[SpmNarrowTileX][SpmNarrowTileY]),
272-
.floo_rsp_o (floo_rsp_out[SpmNarrowTileX][SpmNarrowTileY]),
273-
.floo_wide_i (floo_wide_in[SpmNarrowTileX][SpmNarrowTileY])
274-
);
275-
276-
// Wide SPM tile
277-
localparam int SpmWideTileSamIdx = int'(TopSpmWideSamIdx);
278-
localparam id_t SpmWideTileId = CollectiveSam[SpmWideTileSamIdx].idx.id;
279-
localparam id_t SpmWideTilePhysicalId = SamPhysical[SpmWideTileSamIdx].idx;
280-
localparam int SpmWideTileX = int'(SpmWideTilePhysicalId.x);
281-
localparam int SpmWideTileY = int'(SpmWideTilePhysicalId.y);
282-
283-
spm_tile #(
284-
.axi_aw_chan_t (floo_gwaihir_noc_pkg::axi_wide_out_aw_chan_t),
285-
.axi_w_chan_t (floo_gwaihir_noc_pkg::axi_wide_out_w_chan_t),
286-
.axi_b_chan_t (floo_gwaihir_noc_pkg::axi_wide_out_b_chan_t),
287-
.axi_ar_chan_t (floo_gwaihir_noc_pkg::axi_wide_out_ar_chan_t),
288-
.axi_r_chan_t (floo_gwaihir_noc_pkg::axi_wide_out_r_chan_t),
289-
.axi_to_mem_req_t (floo_gwaihir_noc_pkg::axi_wide_out_req_t),
290-
.axi_to_mem_rsp_t (floo_gwaihir_noc_pkg::axi_wide_out_rsp_t),
291-
.AxiIdWidth (AxiCfgW.InIdWidth),
292-
.AxiDataWidth (AxiCfgW.DataWidth),
293-
.SpmTileSize (SpmWideTileSize),
294-
.SpmWordsPerBank (SpmWideWordsPerBank),
295-
.SpmDataWidth (SpmWideDataWidth),
296-
.SpmNumBanksPerWord(SpmWideNumBanksPerWord),
297-
.SpmNumBankRows (SpmWideNumBankRows),
298-
.IsNarrow (1'b0)
299-
) i_wide_spm_tile (
300-
.clk_i,
301-
.rst_ni,
302-
.test_enable_i(test_mode_i),
303-
.id_i (SpmWideTileId),
304-
.floo_req_o (floo_req_out[SpmWideTileX][SpmWideTileY]),
305-
.floo_rsp_i (floo_rsp_in[SpmWideTileX][SpmWideTileY]),
306-
.floo_wide_o (floo_wide_out[SpmWideTileX][SpmWideTileY]),
307-
.floo_req_i (floo_req_in[SpmWideTileX][SpmWideTileY]),
308-
.floo_rsp_o (floo_rsp_out[SpmWideTileX][SpmWideTileY]),
309-
.floo_wide_i (floo_wide_in[SpmWideTileX][SpmWideTileY])
310-
);
311-
312236
////////////////
313237
// Dummy tile //
314238
////////////////

pyproject.toml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@ dependencies = [
1919

2020
[dependency-groups]
2121
dev = [
22+
"mako>=1.3.10",
23+
"pyyaml>=6.0.3",
2224
"reuse>=6.2.0",
2325
]
2426

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