Inconsistent axi user width

[fischeti]

In the memory tile, the user width that is used by the ATOP resolver to determine the core id is hardcoded to 4 bits:

gwaihir/hw/mem_tile.sv

Lines 19 to 20 in 952bf46

	parameter int unsigned AxiUserAtopMsb = 3,
	parameter int unsigned AxiUserAtopLsb = 0,

This is not ideal since:

1. There are at least 17 "cores" (16 clusters + 1 host core)
2. It is hard coded instead of taken from the generated pkg