Bender.yml

package:
  name: hci
  authors:
    - "Francesco Conti <f.conti@unibo.it>"
    - "Gianna Paulin <pauling@iis.ee.ethz.ch>"
    - "Tobias Riedener <tobiasri@student.ethz.ch>"
    - "Luigi Ghionda <luigi.ghionda2@studio.it>"
    - "Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>"
    - "Sergio Mazzola <smazzola@iis.ee.ethz.ch>"

dependencies:
  hwpe-stream:            { git: "https://github.com/pulp-platform/hwpe-stream.git", version: 1.10.0 }
  cluster_interconnect:   { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 }
  L2_tcdm_hybrid_interco: { git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git", version: 1.0.0 }
  redundancy_cells:       { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase
  common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0 }
  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }

# this is necessary to expose hci_helpers.svh to dependent packages
export_include_dirs:
  - rtl/common

sources:
  - include_dirs:
      - rtl/common
    files:
      # Source files grouped in levels. Files in level 0 have no dependencies on files in this
      # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
      # levels 1 and 0, etc. Files within a level are ordered alphabetically.
      # Level 0
      - rtl/common/hci_package.sv
      - rtl/ecc/hci_ecc_manager_reg_pkg.sv
      # Level 1
      - rtl/common/hci_interfaces.sv
      - rtl/ecc/hci_ecc_manager_reg_top.sv
      # Level 2
      - rtl/core/hci_core_assign.sv
      - rtl/core/hci_core_assign_expand.sv
      - rtl/core/hci_core_cut.sv
      - rtl/core/hci_core_fifo.sv
      - rtl/core/hci_core_mux_dynamic.sv
      - rtl/core/hci_core_mux_static.sv
      - rtl/core/hci_core_mux_ooo.sv
      - rtl/core/hci_core_r_valid_filter.sv
      - rtl/core/hci_core_r_id_filter.sv
      - rtl/core/hci_core_rob.sv
      - rtl/core/hci_core_source.sv
      - rtl/core/hci_core_source_v2.sv
      - rtl/core/hci_core_split.sv
      - rtl/ecc/hci_ecc_dec.sv
      - rtl/ecc/hci_ecc_enc.sv
      - rtl/ecc/hci_ecc_manager.sv
      - rtl/variablelatency/hci_variablelatency_assign.sv
      - rtl/variablelatency/hci_variablelatency_tocore.sv
      - rtl/interco/hci_log_interconnect.sv
      - rtl/interco/deprecated/hci_log_interconnect_l2.sv
      - rtl/interco/hci_new_log_interconnect.sv # `new_XBAR_TCDM` dep. is a private repo
      - rtl/interco/hci_arbiter.sv
      - rtl/interco/hci_arbiter_tree.sv
      - rtl/interco/hci_router_reorder.sv
      - rtl/parity/hci_copy_source.sv
      - rtl/parity/hci_copy_sink.sv
      # Level 3
      - rtl/core/hci_core_sink.sv
      - rtl/ecc/hci_ecc_source.sv
      - rtl/core/hci_core_sink_v2.sv
      - rtl/interco/hci_router.sv
      # Level 4
      - rtl/ecc/hci_ecc_interconnect.sv
      - rtl/ecc/hci_ecc_sink.sv
      - rtl/hci_interconnect.sv

      - target: hci_verif
        include_dirs:
          - target/verif/simvectors/generated
        files:
          # Level 0
          - target/verif/src/tb_hci_pkg.sv
          # Level 1
          - target/verif/src/application_driver.sv
          - target/verif/src/tcdm_banks_wrap.sv
          - target/verif/src/req_gnt_monitor.sv
          - target/verif/src/bandwidth_monitor.sv
          # Level 2
          - target/verif/src/simulation_report.sv
          # Level 3
          - target/verif/src/tb_hci.sv