Release v0.4.0

Author: thommythomaso

CHANGELOG.md

@@ -4,17 +4,34 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
+## 0.4.0 - 2022-11-11
 
-## 0.3.1 - 2022-10.28
+### Changed
+- Bump AXI version to [`v.0.39.0-beta.2`](https://github.com/pulp-platform/axi/releases/tag/v0.39.0-beta.2)
+  [#20](https://github.com/pulp-platform/iDMA/pull/20).
+- Add new protocol capabilities introduced by [#20](https://github.com/pulp-platform/iDMA/pull/20) to the `README.md`.
+
+### Fixed
+- Various fixes; add missing ports in the testbenches, remove stale comments, and remove duplicates
+  in `Bender.yml` [#17](https://github.com/pulp-platform/iDMA/pull/17).
+
+### Added
+- Add `guard.svh`, a simple macro to guard nonsynthesizable code in the iDMA
+  repository [#17](https://github.com/pulp-platform/iDMA/pull/17).
+- Add support for the [OBI v1.5.0](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/obi/OBI-v1.5.0.pdf)
+  protocol [#20](https://github.com/pulp-platform/iDMA/pull/20).
+- Add support for the AXI4 Lite protocol [#20](https://github.com/pulp-platform/iDMA/pull/20).
+
+## 0.3.1 - 2022-10-28
 
 ### Fixed
-- `dma_core_wrap`: Remove parameter `DmaAddrWidth` in `idma_reg64_frontend`. [#16](https://github.com/pulp-platform/iDMA/pull/16).
+- `dma_core_wrap`: Remove parameter `DmaAddrWidth` in `idma_reg64_frontend` [#16](https://github.com/pulp-platform/iDMA/pull/16).
 
-## 0.3.0 - 2022-10.28
+## 0.3.0 - 2022-10-28
 
 ### Fixed
-- Fix the `Aw`-handshaking in the `channel-coupler` module. [#13](https://github.com/pulp-platform/iDMA/pull/13).
-- Minor fixes in `dma_core_wrap` and `idma_reg64_frontend`. [#15](https://github.com/pulp-platform/iDMA/pull/15).
+- Fix the `Aw`-handshaking in the `channel-coupler` module [#13](https://github.com/pulp-platform/iDMA/pull/13).
+- Minor fixes in `dma_core_wrap` and `idma_reg64_frontend` [#15](https://github.com/pulp-platform/iDMA/pull/15).
 
 `dma_core_wrap` has lost the `DmaAddrWidth` parameter rendering `v0.3.0` incompatible to previous
 versions.
@@ -30,10 +47,10 @@ versions.
   - `axi` from `v0.35.1` to `v0.37.0`
   - `common_cells` from `1.21.0` to `1.26.0`
   - `common_verification` from `0.2.0` to `0.2.2`
-- Replace local modules with their upstream versions: [#11](https://github.com/pulp-platform/iDMA/pull/11)., [#12](https://github.com/pulp-platform/iDMA/pull/12).
+- Replace local modules with their upstream versions: [#11](https://github.com/pulp-platform/iDMA/pull/11), [#12](https://github.com/pulp-platform/iDMA/pull/12).
 
 ### Fixed
-- Fix the `Aw`-handshaking in the `channel-coupler` module. [#10](https://github.com/pulp-platform/iDMA/pull/10).
+- Fix the `Aw`-handshaking in the `channel-coupler` module [#10](https://github.com/pulp-platform/iDMA/pull/10).
 - Fix missing python modules in GitHub CI.
 - Fix wrong date format as well as missing indentation in `CHANGELOG.md`.
 

README.md

@@ -8,15 +8,19 @@ computing systems. iDMA is part of the [PULP (Parallel Ultra-Low-Power) platform
 where it is used as a cluster level DMA in the [Snitch Cluster](https://github.com/pulp-platform/snitch)
 and in the [PULP Cluster](https://github.com/pulp-platform/pulp).
 
-iDMA currently implements AXI4[+ATOPs from AXI5](https://github.com/pulp-platform/axi).
+iDMA currently implements the following protocols:
+- [AXI4](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)[+ATOPs from AXI5](https://github.com/pulp-platform/axi)
+- [AXI4 Lite](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)
+- [OBI v1.5.0](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/obi/OBI-v1.5.0.pdf)
+
 
 ## Modular Architecture
 iDMA is centered around the idea to split the DMA engine in 3 distinct parts:
 - **Frontend:** The frontend implements the communication with the platform and emits transfer requests
 - **Midend:** Midend(s) transform a transfer request from the frontend to generic 1D transfers,
               which can be handled by the backend.
 - **Bakend:** The backend gets a 1D transfer `(src_addr, dst_addr, length)` and executes it
-              on the AXI4 manager interface.
+              on the transport protocol's manager interface.
 
 The interface between the parts are well-defined, making it easy to adapt to a new system or to add
 new capabilities.
@@ -43,7 +47,8 @@ various tools are required.
 - [`morty >= v0.6.0`](https://github.com/zarubaf/morty)
 - [`Verilator = v4.202`](https://www.veripool.org/verilator)
 - [`Verible >= v0.0-1051-gd4cd328`](https://github.com/chipsalliance/verible)
-- `Python3 >= 3.8` including some the libraries listed in [`requirements.txt`](requirements.txt)
+- [`Python3 >= 3.8`](https://www.python.org/downloads/) including some the libraries listed
+  in [`requirements.txt`](requirements.txt)
 
 ### Building the Documentation
 Use `make doc` to build the documentation. The output is located at `doc/build`.

VERSION

@@ -1 +1 @@
-0.3.1
+0.4.0