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test: Add address-gen transpose regressions
TBs drive a transpose request through idma_transpose_midend (so its stride expansion is exercised) into idma_nd_midend + a stock rw_axi / rw_obi backend, checking out_T[c][r]==in[r][c] with no compute engine. Cover int8/fp16/fp32, square/rect/odd, DataWidth 32 and 64; OBI uses native obi_sim_mem. Wired into idma.mk (idma_sim_tb_idma_addrgen_transpose[_obi]).
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‎Bender.yml‎

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@@ -135,6 +135,8 @@ sources:
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- target/rtl/tb_idma_generated.sv
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- test/tb_idma_transpose_nd.sv
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- test/tb_idma_transpose_b2b.sv
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- test/tb_idma_addrgen_transpose.sv
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- test/tb_idma_addrgen_transpose_obi.sv
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# Multi-head directed backend testbenches
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- target: multihead

‎idma.mk‎

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@@ -387,6 +387,21 @@ idma_sim_tb_idma_transpose_b2b: $(IDMA_VSIM_DIR)/compile.tcl
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=32 tb_idma_transpose_b2b -do "run -all; quit"
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=64 tb_idma_transpose_b2b -do "run -all; quit"
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# Address-gen transpose: idma_transpose_midend (AddrGen) -> idma_nd_midend ->
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# stock rw_axi / rw_obi backend. No compute engine. TB sweeps geometries; one
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# run per bus width.
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.PHONY: idma_sim_tb_idma_addrgen_transpose
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idma_sim_tb_idma_addrgen_transpose: $(IDMA_VSIM_DIR)/compile.tcl
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=32 tb_idma_addrgen_transpose -do "run -all; quit"
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=64 tb_idma_addrgen_transpose -do "run -all; quit"
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.PHONY: idma_sim_tb_idma_addrgen_transpose_obi
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idma_sim_tb_idma_addrgen_transpose_obi: $(IDMA_VSIM_DIR)/compile.tcl
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=32 tb_idma_addrgen_transpose_obi -do "run -all; quit"
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gDataWidth=64 tb_idma_addrgen_transpose_obi -do "run -all; quit"
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.PHONY: idma_sim_tb_idma_transpose_midend
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idma_sim_tb_idma_transpose_midend: $(IDMA_VSIM_DIR)/compile.tcl
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cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"

‎test/tb_idma_addrgen_transpose.sv‎

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// Copyright 2026 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Authors:
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// - Daniel Keller <dankeller@iis.ee.ethz.ch>
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// Address-gen transpose proof: NO compute engine. A plain rw_axi backend
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// transposes an M x N matrix purely via a 2D ND program with swapped strides
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// and a one-element (EB-byte) inner burst. out_T[c][r] = in[r][c], dst is a
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// contiguous N x M transpose (no padding). Validates that iDMA's read->FIFO->
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// write datapath transposes by addressing alone, the basis for the OBI/TCDM
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// multi-write transpose path.
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`include "axi/typedef.svh"
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`include "idma/typedef.svh"
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module tb_idma_addrgen_transpose
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import idma_pkg::*;
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#(
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parameter int unsigned DataWidth = 32,
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parameter int unsigned AddrWidth = 32,
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parameter int unsigned UserWidth = 1,
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parameter int unsigned AxiIdWidth = 12,
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parameter int unsigned TFLenWidth = 32,
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parameter int unsigned BufferDepth = 3
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);
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localparam time TA = 1ns;
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localparam time TT = 9ns;
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localparam time TCK = 10ns;
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localparam int unsigned StrbWidth = DataWidth / 8;
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localparam int unsigned AxIF = 8;
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// base burst = 1 element (dim 0); two repetition dims (col, row) => NumDim=3
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localparam int unsigned NumDim = 3;
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localparam logic [NumDim-1:0][31:0] RepWidths = '{default: 32'd16};
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// Geometry cases (M, N, EB): square, rectangular, odd, int8/fp16/fp32.
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localparam int unsigned NCases = 8;
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localparam int unsigned Cases [NCases][3] = '{
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'{ 4, 4, 1}, '{ 8, 8, 1}, '{ 8, 4, 1}, '{ 4, 8, 1},
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'{ 6, 5, 1}, '{ 5, 7, 2}, '{ 3, 9, 4}, '{16, 16, 1}
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};
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// ── Types ──
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typedef logic [AddrWidth-1:0] addr_t;
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typedef logic [DataWidth-1:0] data_t;
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typedef logic [StrbWidth-1:0] strb_t;
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typedef logic [AxiIdWidth-1:0] id_t;
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typedef logic [UserWidth-1:0] user_t;
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typedef logic [TFLenWidth-1:0] tf_len_t;
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typedef logic [31:0] reps_t;
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`AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t)
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`AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t)
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`AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t)
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`AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t)
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`AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t)
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`AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t)
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`AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t)
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`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t)
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`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t)
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`IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, addr_t)
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typedef struct packed { axi_ar_chan_t ar_chan; } axi_read_meta_channel_t;
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typedef struct packed { axi_read_meta_channel_t axi; } read_meta_channel_t;
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typedef struct packed { axi_aw_chan_t aw_chan; } axi_write_meta_channel_t;
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typedef struct packed { axi_write_meta_channel_t axi; } write_meta_channel_t;
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// ── Signals ──
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logic clk, rst_n;
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idma_req_t idma_req; logic req_valid, req_ready;
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idma_rsp_t idma_rsp; logic rsp_valid, rsp_ready;
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idma_eh_req_t idma_eh_req; logic eh_req_valid, eh_req_ready;
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idma_nd_req_t tp_req; logic tp_valid, tp_ready; // TB -> transpose midend
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idma_nd_req_t nd_req; logic nd_req_valid, nd_req_ready; // transpose midend -> nd midend
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idma_rsp_t nd_rsp; logic nd_rsp_valid, nd_rsp_ready;
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axi_req_t axi_read_req, axi_write_req, axi_req, axi_req_mem;
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axi_rsp_t axi_read_rsp, axi_write_rsp, axi_rsp, axi_rsp_mem;
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idma_busy_t busy; logic nd_busy;
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assign idma_eh_req = '0;
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assign eh_req_valid = 1'b0;
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// ── Clock / reset ──
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clk_rst_gen #(.ClkPeriod(TCK), .RstClkCycles(1)) i_clk_rst_gen (.clk_o(clk), .rst_no(rst_n));
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// ── AXI sim memory (read+write joined) ──
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axi_rw_join #(.axi_req_t(axi_req_t), .axi_resp_t(axi_rsp_t)) i_axi_rw_join (
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.clk_i(clk), .rst_ni(rst_n),
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.slv_read_req_i(axi_read_req), .slv_read_resp_o(axi_read_rsp),
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.slv_write_req_i(axi_write_req), .slv_write_resp_o(axi_write_rsp),
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.mst_req_o(axi_req), .mst_resp_i(axi_rsp)
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);
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assign axi_req_mem = axi_req;
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assign axi_rsp = axi_rsp_mem;
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axi_sim_mem #(
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.AddrWidth(AddrWidth), .DataWidth(DataWidth), .IdWidth(AxiIdWidth), .UserWidth(UserWidth),
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.axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t),
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.WarnUninitialized(1'b0), .ClearErrOnAccess(1'b1), .ApplDelay(TA), .AcqDelay(TT)
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) i_axi_sim_mem (
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.clk_i(clk), .rst_ni(rst_n), .axi_req_i(axi_req_mem), .axi_rsp_o(axi_rsp_mem),
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.mon_r_last_o(), .mon_r_beat_count_o(), .mon_r_user_o(), .mon_r_id_o(),
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.mon_r_data_o(), .mon_r_addr_o(), .mon_r_valid_o(),
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.mon_w_last_o(), .mon_w_beat_count_o(), .mon_w_user_o(), .mon_w_id_o(),
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.mon_w_data_o(), .mon_w_addr_o(), .mon_w_valid_o()
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);
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// ── Transpose midend (RTL UNDER TEST): expands the transpose request into the
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// swapped-stride ND program; the nd_midend + backend just execute it ──
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idma_transpose_midend #(
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.NumDim(NumDim), .AddrGenTranspose(1'b1), .StrbWidth(StrbWidth),
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.addr_t(addr_t), .idma_nd_req_t(idma_nd_req_t)
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) i_xpose_midend (
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.nd_req_i(tp_req), .valid_i(tp_valid), .ready_o(tp_ready),
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.nd_req_o(nd_req), .valid_o(nd_req_valid), .ready_i(nd_req_ready)
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);
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// ── ND midend: walks the swapped-stride program into 1-element bursts ──
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idma_nd_midend #(
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.NumDim(NumDim), .addr_t(addr_t), .idma_req_t(idma_req_t),
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.idma_rsp_t(idma_rsp_t), .idma_nd_req_t(idma_nd_req_t), .RepWidths(RepWidths)
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) i_nd_midend (
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.clk_i(clk), .rst_ni(rst_n),
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.nd_req_i(nd_req), .nd_req_valid_i(nd_req_valid), .nd_req_ready_o(nd_req_ready),
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.nd_rsp_o(nd_rsp), .nd_rsp_valid_o(nd_rsp_valid), .nd_rsp_ready_i(nd_rsp_ready),
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.burst_req_o(idma_req), .burst_req_valid_o(req_valid), .burst_req_ready_i(req_ready),
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.burst_rsp_i(idma_rsp), .burst_rsp_valid_i(rsp_valid), .burst_rsp_ready_o(rsp_ready),
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.busy_o(nd_busy)
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);
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// ── Backend (rw_axi), plain copy — NO compute engine ──
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idma_backend_rw_axi #(
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.CombinedShifter(1'b0), .DataWidth(DataWidth), .AddrWidth(AddrWidth), .AxiIdWidth(AxiIdWidth),
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.UserWidth(UserWidth), .TFLenWidth(TFLenWidth), .MaskInvalidData(1'b1), .BufferDepth(BufferDepth),
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.RAWCouplingAvail(1'b1), .HardwareLegalizer(1'b1), .RejectZeroTransfers(1'b1),
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.ErrorCap(idma_pkg::NO_ERROR_HANDLING), .PrintFifoInfo(1'b0), .NumAxInFlight(AxIF), .MemSysDepth(0),
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.idma_req_t(idma_req_t), .idma_rsp_t(idma_rsp_t), .idma_eh_req_t(idma_eh_req_t),
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.idma_busy_t(idma_busy_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t),
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.write_meta_channel_t(write_meta_channel_t), .read_meta_channel_t(read_meta_channel_t)
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) i_idma_backend (
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.clk_i(clk), .rst_ni(rst_n), .testmode_i(1'b0),
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.idma_req_i(idma_req), .req_valid_i(req_valid), .req_ready_o(req_ready),
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.idma_rsp_o(idma_rsp), .rsp_valid_o(rsp_valid), .rsp_ready_i(rsp_ready),
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.idma_eh_req_i(idma_eh_req), .eh_req_valid_i(eh_req_valid), .eh_req_ready_o(eh_req_ready),
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.axi_read_req_o(axi_read_req), .axi_read_rsp_i(axi_read_rsp),
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.axi_write_req_o(axi_write_req), .axi_write_rsp_i(axi_write_rsp), .busy_o(busy)
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);
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stream_watchdog #(.NumCycles(4000)) i_r_wd (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_rsp.r_valid), .ready_i(axi_req.r_ready));
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stream_watchdog #(.NumCycles(4000)) i_w_wd (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready));
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// ── Stimulus + check via sim-memory backdoor ──
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addr_t sb = 'h0000_1000;
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addr_t db = 'h0000_8000;
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task automatic wr_mem(input addr_t a, input logic [7:0] d); i_axi_sim_mem.mem[a] = d; endtask
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function automatic logic [7:0] rd_mem(input addr_t a);
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return i_axi_sim_mem.mem.exists(a) ? i_axi_sim_mem.mem[a] : 8'hxx;
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endfunction
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// Run one M x N transpose of EB-byte elements; returns the mismatch count.
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task automatic run_case(input int unsigned m, input int unsigned n, input int unsigned eb,
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output int unsigned errs);
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errs = 0;
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// init source matrix (row-major, m x n elements of eb bytes), unique fingerprint
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for (int unsigned r = 0; r < m; r++)
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for (int unsigned c = 0; c < n; c++)
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for (int unsigned b = 0; b < eb; b++)
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wr_mem(sb + (r*n + c)*eb + b, 8'((( (r*n+c)*eb + b )*7 + 3) & 8'hFF));
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// sentinel-fill the contiguous N x M dst
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for (int unsigned k = 0; k < n*m*eb; k++) wr_mem(db + k, 8'hCC);
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// Drive a transpose request THROUGH idma_transpose_midend (it computes the
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// swapped-stride program); the TB sets only the compute fields + addresses,
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// NOT the strides — so the midend's expansion is what gets exercised.
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tp_req = '0;
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tp_req.burst_req.src_addr = sb;
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tp_req.burst_req.dst_addr = db;
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tp_req.burst_req.opt.src_protocol = idma_pkg::AXI;
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tp_req.burst_req.opt.dst_protocol = idma_pkg::AXI;
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tp_req.burst_req.opt.src.burst = axi_pkg::BURST_INCR;
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tp_req.burst_req.opt.dst.burst = axi_pkg::BURST_INCR;
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tp_req.burst_req.opt.beo.decouple_rw = 1'b1;
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tp_req.burst_req.opt.beo.decouple_aw = 1'b1;
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tp_req.burst_req.opt.last = 1'b1;
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tp_req.burst_req.opt.compute.enable = 1'b1;
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tp_req.burst_req.opt.compute.op = idma_pkg::COMPUTE_TRANSPOSE;
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tp_req.burst_req.opt.compute.params.transpose.mode = 2'(eb == 4 ? 2 : eb == 2 ? 1 : 0);
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tp_req.burst_req.opt.compute.params.transpose.tensor_m = 12'(m);
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tp_req.burst_req.opt.compute.params.transpose.tensor_n = 12'(n);
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$display("[AG] case %0dx%0d EB=%0d (via transpose_midend, %0d elements)", m, n, eb, m*n);
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tp_valid = 1'b1;
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do @(posedge clk); while (!tp_ready);
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tp_valid = 1'b0;
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tp_req = '0;
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while (!(nd_rsp_valid && nd_rsp_ready)) @(posedge clk);
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repeat (20) @(posedge clk);
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// check: out_T[c][r] == in[r][c], dst contiguous N x M (pitch M)
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for (int unsigned c = 0; c < n; c++)
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for (int unsigned r = 0; r < m; r++)
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for (int unsigned b = 0; b < eb; b++) begin
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automatic logic [7:0] got = rd_mem(db + (c*m + r)*eb + b);
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automatic logic [7:0] exp = rd_mem(sb + (r*n + c)*eb + b);
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if (got !== exp) begin
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errs++;
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if (errs <= 12) $display("[AG] MISMATCH out_T[%0d][%0d].b%0d=%02h exp %02h", c, r, b, got, exp);
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end
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end
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endtask
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initial begin
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automatic int unsigned total = 0;
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automatic int unsigned ce;
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tp_valid = 1'b0; nd_rsp_ready = 1'b1; tp_req = '0;
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@(posedge rst_n);
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repeat (5) @(posedge clk);
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for (int unsigned k = 0; k < NCases; k++) begin
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if (Cases[k][2] > StrbWidth) continue;
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run_case(Cases[k][0], Cases[k][1], Cases[k][2], ce);
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if (ce == 0) $display("[AG] PASS: %0dx%0d EB=%0d", Cases[k][0], Cases[k][1], Cases[k][2]);
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else $display("[AG] FAIL: %0dx%0d EB=%0d (%0d mismatches)", Cases[k][0], Cases[k][1], Cases[k][2], ce);
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total += ce;
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end
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if (total == 0) $display("[AG] ALL PASS (%0d cases, StrbWidth=%0d)", NCases, StrbWidth);
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else $fatal(1, "[AG] FAIL: %0d total mismatches", total);
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repeat (5) @(posedge clk);
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$finish();
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end
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initial begin #100_000_000; $fatal(1, "[AG] timeout"); end
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endmodule

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