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| 1 | +/* |
| 2 | + * Copyright (C) 2018 ETH Zurich and University of Bologna |
| 3 | + * |
| 4 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | + * you may not use this file except in compliance with the License. |
| 6 | + * You may obtain a copy of the License at |
| 7 | + * |
| 8 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | + * |
| 10 | + * Unless required by applicable law or agreed to in writing, software |
| 11 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | + * See the License for the specific language governing permissions and |
| 14 | + * limitations under the License. |
| 15 | + */ |
| 16 | + |
| 17 | +#ifndef __ARCHI_KAIROS_APB_SOC_H__ |
| 18 | +#define __ARCHI_KAIROS_APB_SOC_H__ |
| 19 | + |
| 20 | +#define APB_SOC_BOOT_OTHER 0 |
| 21 | +#define APB_SOC_BOOT_JTAG 1 |
| 22 | +#define APB_SOC_BOOT_SPI 2 |
| 23 | +#define APB_SOC_BOOT_ROM 3 |
| 24 | +#define APB_SOC_BOOT_PRELOAD 4 |
| 25 | +#define APB_SOC_BOOT_HYPER 5 |
| 26 | +#define APB_SOC_BOOT_SPIM 6 |
| 27 | +#define APB_SOC_BOOT_SPIM_QPI 7 |
| 28 | + |
| 29 | +#define APB_SOC_PLT_OTHER 0 |
| 30 | +#define APB_SOC_PLT_FPGA 1 |
| 31 | +#define APB_SOC_PLT_RTL 2 |
| 32 | +#define APB_SOC_PLT_VP 3 |
| 33 | +#define APB_SOC_PLT_CHIP 4 |
| 34 | + |
| 35 | +//PADs configuration is made of 8bits out of which only the first 6 are used |
| 36 | +//bit0 enable pull UP |
| 37 | +//bit1 enable pull DOWN |
| 38 | +//bit2 enable ST |
| 39 | +//bit3 enable SlewRate Limit |
| 40 | +//bit4..5 Driving Strength |
| 41 | +//bit6..7 not used |
| 42 | + |
| 43 | +#define APB_SOC_BOOTADDR_OFFSET 0x04 |
| 44 | +#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0] |
| 45 | +#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment |
| 46 | +#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment |
| 47 | +#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment |
| 48 | + |
| 49 | +#define APB_SOC_PADFUN0_OFFSET 0x10 |
| 50 | +#define APB_SOC_PADCFG0_OFFSET 0x20 |
| 51 | + |
| 52 | +#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30]) |
| 53 | +#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4) |
| 54 | +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) |
| 55 | +#define APB_SOC_PADFUN_SIZE 2 |
| 56 | +#define ARCHI_APB_SOC_PADFUN_NB 4 |
| 57 | +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) |
| 58 | + |
| 59 | +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) |
| 60 | +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) |
| 61 | +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) |
| 62 | +#define APB_SOC_PADCFG_SIZE 8 |
| 63 | +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) |
| 64 | + |
| 65 | +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) |
| 66 | +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) |
| 67 | +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot |
| 68 | +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment |
| 69 | +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) |
| 70 | +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment |
| 71 | +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) |
| 72 | +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment |
| 73 | +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) |
| 74 | +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) |
| 75 | +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment |
| 76 | +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment |
| 77 | +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment |
| 78 | +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment |
| 79 | +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment |
| 80 | +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment |
| 81 | +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) |
| 82 | +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) |
| 83 | +#define APB_SOC_PADS_CONFIG 0xC4 |
| 84 | + |
| 85 | +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 |
| 86 | + |
| 87 | +#define APB_SOC_JTAG_REG_EXT_BIT 8 |
| 88 | +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 |
| 89 | + |
| 90 | +#define APB_SOC_JTAG_REG_LOC_BIT 0 |
| 91 | +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 |
| 92 | + |
| 93 | +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) |
| 94 | +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) |
| 95 | + |
| 96 | +#define APB_SOC_STATUS_EOC_BIT 31 |
| 97 | +#define APB_SOC_NB_CORE_BIT 16 |
| 98 | + |
| 99 | + |
| 100 | +#define APB_SOC_BYPASS_OFFSET 0x70 |
| 101 | + |
| 102 | +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 |
| 103 | +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 |
| 104 | +#define APB_SOC_BYPASS_USER0_BIT 14 |
| 105 | +#define APB_SOC_BYPASS_USER1_BIT 15 |
| 106 | + |
| 107 | + |
| 108 | +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 |
| 109 | +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 |
| 110 | +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 |
| 111 | +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC |
| 112 | + |
| 113 | + |
| 114 | +#define APB_SOC_FLL_CTRL_SOC_BIT 0 |
| 115 | +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 |
| 116 | +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 |
| 117 | + |
| 118 | + |
| 119 | +#define APB_SOC_RTC_OFFSET 0x1D0 |
| 120 | + |
| 121 | +#endif |
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