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Switched unpacked arrays used for redundancy to packed arrays.
1 parent 5e07378 commit 1413b1f

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5 files changed

+60
-81
lines changed

5 files changed

+60
-81
lines changed

‎rtl/time_redundancy/redundancy_controller.sv

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -47,16 +47,15 @@ module redundancy_controller # (
4747
);
4848

4949
// Redundant versions of output signals
50-
logic valid_ov[REP];
51-
logic ready_ov[REP];
52-
logic busy_ov[REP];
53-
logic enable_ov[REP];
54-
logic flush_ov[REP];
50+
logic [REP-1:0] valid_ov;
51+
logic [REP-1:0] ready_ov;
52+
logic [REP-1:0] busy_ov;
53+
logic [REP-1:0] enable_ov;
54+
logic [REP-1:0] flush_ov;
55+
logic [REP-1:0] timeout_v;
5556

56-
logic enable_v[REP], enable_d[REP], enable_q[REP];
57-
logic [$clog2(LockTimeout)-1:0] counter_v[REP], counter_d[REP], counter_q[REP];
58-
59-
logic timout_v[REP];
57+
logic [REP-1:0] enable_b, enable_v, enable_d, enable_q;
58+
logic [REP-1:0][$clog2(LockTimeout)-1:0] counter_b, counter_v, counter_d, counter_q;
6059

6160
for (genvar r = 0; r < REP; r++) begin: gen_next_state
6261
always_comb begin
@@ -70,13 +69,13 @@ module redundancy_controller # (
7069
// If the unit is stalled e.g. nothing gets out during for the timeout, then trickle new operations in to unstall it
7170
if (counter_q[r] > LockTimeout) begin
7271
counter_v[r] = 0;
73-
timout_v[r] = 1;
72+
timeout_v[r] = 1;
7473
end else if (valid_i && enable_q[r] && !enable_i) begin
7574
counter_v[r] = counter_q[r] + 1;
76-
timout_v[r] = 0;
75+
timeout_v[r] = 0;
7776
end else begin
7877
counter_v[r] = 0;
79-
timout_v[r] = 0;
78+
timeout_v[r] = 0;
8079
end
8180
end
8281
end
@@ -91,8 +90,6 @@ module redundancy_controller # (
9190
end
9291

9392
// Generate default case
94-
logic enable_b[REP];
95-
logic [$clog2(LockTimeout)-1:0] counter_b[REP];
9693
for (genvar r = 0; r < REP; r++) begin: gen_default_state
9794
assign enable_b[r] = '0;
9895
assign counter_b[r] = '0;
@@ -106,7 +103,7 @@ module redundancy_controller # (
106103
always_comb begin
107104
enable_ov[r] = enable_q[r];
108105

109-
if ((enable_q[r] == enable_i) || timout_v[r]) begin
106+
if ((enable_q[r] == enable_i) || timeout_v[r]) begin
110107
valid_ov[r] = valid_i;
111108
ready_ov[r] = ready_i;
112109
busy_ov[r] = busy_i;

‎rtl/time_redundancy/time_DMR_end.sv

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -88,10 +88,10 @@ module time_DMR_end # (
8888
);
8989

9090
// Redundant Output signals
91-
logic ready_ov[REP];
92-
logic valid_ov[REP];
93-
logic needs_retry_ov[REP];
94-
logic fault_detected_ov[REP];
91+
logic [REP-1:0] ready_ov;
92+
logic [REP-1:0] valid_ov;
93+
logic [REP-1:0] needs_retry_ov;
94+
logic [REP-1:0] fault_detected_ov;
9595

9696
/////////////////////////////////////////////////////////////////////////////////
9797
// Storage of incomming results and generating good output data
@@ -148,8 +148,8 @@ module time_DMR_end # (
148148
/////////////////////////////////////////////////////////////////////////////////
149149
// Logic to find out what we should do with our data based on same / not same
150150

151-
logic new_element_arrived_v[REP];
152-
logic data_usable_v[REP];
151+
logic [REP-1:0] new_element_arrived_v;
152+
logic [REP-1:0] data_usable_v;
153153

154154
// Flag Combinatorial Logic
155155
for (genvar r = 0; r < REP; r++) begin: gen_data_flags
@@ -166,8 +166,8 @@ module time_DMR_end # (
166166
// State machine to figure out handshake
167167

168168
typedef enum logic [0:0] {BASE, WAIT_FOR_READY} state_t;
169-
state_t state_v[REP], state_d[REP], state_q[REP];
170-
logic valid_internal_v[REP], lock_internal_v[REP];
169+
state_t [REP-1:0] state_b, state_v, state_d, state_q;
170+
logic [REP-1:0] valid_internal_v, lock_internal_v;
171171

172172
// Special State Description:
173173
// Wait for Ready: We got some data that is usable, but downstream can't use it yet
@@ -200,7 +200,6 @@ module time_DMR_end # (
200200
end
201201

202202
// Generate default cases
203-
state_t state_b[REP];
204203
for (genvar r = 0; r < REP; r++) begin: gen_default_state
205204
assign state_b[r] = BASE;
206205
end
@@ -244,8 +243,8 @@ module time_DMR_end # (
244243
///////////////////////////////////////////////////////////////////////////////////////////////////
245244
// State machine to lock / unlock Arbitrator with Watchdog timer
246245

247-
logic lock_v[REP], lock_d[REP], lock_q[REP];
248-
logic [$clog2(LockTimeout)-1:0] counter_v[REP], counter_d[REP], counter_q[REP];
246+
logic [REP-1:0] lock_b, lock_v, lock_d, lock_q;
247+
logic [REP-1:0][$clog2(LockTimeout)-1:0] counter_b, counter_v, counter_d, counter_q;
249248

250249
// Next State Combinatorial Logic
251250
for (genvar r = 0; r < REP; r++) begin: gen_lock_next_state
@@ -283,8 +282,6 @@ module time_DMR_end # (
283282
assign lock_o = lock_d[0];
284283

285284
// Default state
286-
logic lock_b[REP];
287-
logic [$clog2(LockTimeout)-1:0] counter_b[REP];
288285
for (genvar r = 0; r < REP; r++) begin: gen_lock_default_state
289286
assign lock_b[r] = '0;
290287
assign counter_b[r] = '0;
@@ -300,7 +297,7 @@ module time_DMR_end # (
300297
logic id_fault_q;
301298
assign id_fault_q = ^id_q;
302299

303-
logic [2 ** (IDSize-1)-1:0] recently_seen_v[REP], recently_seen_d[REP], recently_seen_q[REP];
300+
logic [REP-1:0][2 ** (IDSize-1)-1:0] recently_seen_b, recently_seen_v, recently_seen_d, recently_seen_q;
304301

305302
for (genvar r = 0; r < REP; r++) begin: gen_deduplication_next_state
306303
always_comb begin: gen_deduplication_next_state_comb
@@ -322,7 +319,6 @@ module time_DMR_end # (
322319
end
323320

324321
// Default state
325-
logic [2 ** (IDSize-1)-1:0] recently_seen_b[REP];
326322
for (genvar r = 0; r < REP; r++) begin: gen_deduplication_default_state
327323
assign recently_seen_b[r] = ~'0; // All 1s!
328324
end
@@ -355,14 +351,13 @@ module time_DMR_end # (
355351
// In a non-error case, we should have a full same signal every other cycle
356352
// So if that is not the case we had a fault.
357353

358-
logic fault_detected_d[REP], fault_detected_q[REP];
354+
logic [REP-1:0] fault_detected_b, fault_detected_d, fault_detected_q;
359355

360356
for (genvar r = 0; r < REP; r++) begin: gen_flag_next_state
361357
assign fault_detected_d[r] = ~|full_same[1:0] & valid_i;;
362358
end
363359

364360
// Default state
365-
logic fault_detected_b[REP];
366361
for (genvar r = 0; r < REP; r++) begin: gen_flag_default_state
367362
assign fault_detected_b[r] = '0;
368363
end

‎rtl/time_redundancy/time_DMR_start.sv

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -76,19 +76,19 @@ module time_DMR_start # (
7676
input logic ready_i
7777
);
7878
// Redundant Output signals
79-
logic [IDSize-1:0] next_id_ov[REP];
80-
logic ready_ov[REP];
81-
logic valid_ov[REP];
79+
logic [REP-1:0][IDSize-1:0] next_id_ov;
80+
logic [REP-1:0] ready_ov;
81+
logic [REP-1:0] valid_ov;
8282

8383
// State machine TLDR
8484
// - counting the state from 0 to 2 if the handshake is good
8585
// - counting the ID up whenever the state goes back to 0
8686

8787
// Next State Combinatorial Logic
8888
typedef enum logic [1:0] {STORE_AND_SEND, SEND, REPLICATE} state_t;
89-
state_t state_v[REP], state_d[REP], state_q[REP];
90-
DataType data_v[REP], data_d[REP], data_q[REP];
91-
logic [IDSize-1:0] id_v[REP], id_d[REP], id_q[REP];
89+
state_t [REP-1:0] state_b, state_v, state_d, state_q;
90+
DataType [REP-1:0] data_b, data_v, data_d, data_q;
91+
logic [REP-1:0][IDSize-1:0] id_b, id_v, id_d, id_q;
9292

9393
for (genvar r = 0; r < REP; r++) begin: gen_next_state
9494
always_comb begin: gen_next_state_comb
@@ -147,10 +147,6 @@ module time_DMR_start # (
147147
end
148148

149149
// Generate default cases
150-
state_t state_b[REP];
151-
DataType data_b[REP];
152-
logic [IDSize-1:0] id_b[REP];
153-
154150
for (genvar r = 0; r < REP; r++) begin: gen_default_state
155151
assign state_b[r] = STORE_AND_SEND;
156152
assign data_b[r] = 0;

‎rtl/time_redundancy/time_TMR_end.sv

Lines changed: 25 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -82,9 +82,9 @@ module time_TMR_end # (
8282
);
8383

8484
// Redundant Output signals
85-
logic ready_ov[REP];
86-
logic valid_ov[REP];
87-
logic fault_detected_ov[REP];
85+
logic [REP-1:0] ready_ov;
86+
logic [REP-1:0] valid_ov;
87+
logic [REP-1:0] fault_detected_ov;
8888

8989
/////////////////////////////////////////////////////////////////////////////////
9090
// Storage of incomming results and generating good output data
@@ -164,16 +164,16 @@ module time_TMR_end # (
164164

165165
///////////////////////////////////////////////////////////////////////////////////////////////////
166166
// State machine to figure out handshake
167-
logic lock_internal_v[REP];
167+
logic [REP-1:0] lock_internal_v;
168168

169169
if (EarlyValidEnable) begin: gen_early_valid_statemachine
170170

171171
// Input signal reassignment to make state machine more readable
172-
logic element_needs_shift_v[REP];
173-
logic new_element_arrived_v[REP];
174-
logic element_in_input_v[REP];
175-
logic element_relies_on_input_v[REP];
176-
logic data_usable_v[REP];
172+
logic [REP-1:0] element_needs_shift_v;
173+
logic [REP-1:0] new_element_arrived_v;
174+
logic [REP-1:0] element_in_input_v;
175+
logic [REP-1:0] element_relies_on_input_v;
176+
logic [REP-1:0] data_usable_v;
177177

178178
for (genvar r = 0; r < REP; r++) begin: gen_data_flags
179179
always_comb begin: gen_data_flags_comb
@@ -208,7 +208,7 @@ module time_TMR_end # (
208208
// WAIT_FOR_DATA: We got some pieces of data that should belong together but they are not the same
209209
// -> We try to collect one more piece of the same data and then send it downstream
210210
typedef enum logic [1:0] {BASE, WAIT_FOR_READY, WAIT_FOR_VALID, WAIT_FOR_DATA} state_t;
211-
state_t state_v[REP], state_d[REP], state_q[REP];
211+
state_t [REP-1:0] state_b, state_v, state_d, state_q;
212212

213213

214214
// Next State Combinatorial Logic
@@ -266,7 +266,6 @@ module time_TMR_end # (
266266
end
267267

268268
// Generate default cases
269-
state_t state_b[REP];
270269
for (genvar r = 0; r < REP; r++) begin: gen_default_state
271270
assign state_b[r] = WAIT_FOR_VALID;
272271
end
@@ -308,11 +307,11 @@ module time_TMR_end # (
308307
end else begin : gen_late_valid_statemachine
309308

310309
// Input signal reassignment to make state machine more readable
311-
logic new_id_arrived_v[REP];
312-
logic id_in_input_v[REP];
313-
logic id_all_same_v[REP];
314-
logic id_all_cover_v[REP];
315-
logic data_usable_v[REP];
310+
logic [REP-1:0] new_id_arrived_v;
311+
logic [REP-1:0] id_in_input_v;
312+
logic [REP-1:0] id_all_same_v;
313+
logic [REP-1:0] id_all_cover_v;
314+
logic [REP-1:0] data_usable_v;
316315

317316
for (genvar r = 0; r < REP; r++) begin: gen_data_flags
318317
always_comb begin: gen_data_flags_comb
@@ -341,7 +340,7 @@ module time_TMR_end # (
341340
// WAIT_FOR_VALID_X2: We have recieved three fully usable pieces of data
342341
// -> We need to wait for at least two new data elements before data can be valid again
343342
typedef enum logic [1:0] {BASE, WAIT_FOR_READY, WAIT_FOR_VALID, WAIT_FOR_VALID_X2} state_t;
344-
state_t state_v[REP], state_d[REP], state_q[REP];
343+
state_t [REP-1:0] state_b, state_v, state_d, state_q;
345344

346345
// Next State Combinatorial Logic
347346
for (genvar r = 0; r < REP; r++) begin: gen_next_state
@@ -394,7 +393,6 @@ module time_TMR_end # (
394393
end
395394

396395
// Generate default cases
397-
state_t state_b[REP];
398396
for (genvar r = 0; r < REP; r++) begin: gen_default_state
399397
assign state_b[r] = WAIT_FOR_VALID;
400398
end
@@ -438,8 +436,8 @@ module time_TMR_end # (
438436
///////////////////////////////////////////////////////////////////////////////////////////////////
439437
// State machine to lock / unlock Arbitrator with Watchdog timer
440438

441-
logic lock_v[REP], lock_d[REP], lock_q[REP];
442-
logic [$clog2(LockTimeout)-1:0] counter_v[REP], counter_d[REP], counter_q[REP];
439+
logic [REP-1:0] lock_b, lock_v, lock_d, lock_q;
440+
logic [REP-1:0][$clog2(LockTimeout)-1:0] counter_b, counter_v, counter_d, counter_q;
443441

444442
// Next State Combinatorial Logic
445443
for (genvar r = 0; r < REP; r++) begin: gen_lock_next_state
@@ -477,16 +475,14 @@ module time_TMR_end # (
477475
assign lock_o = lock_d[0];
478476

479477
// Default state
480-
logic lock_base[REP];
481-
logic [$clog2(LockTimeout)-1:0] counter_base[REP];
482478
for (genvar r = 0; r < REP; r++) begin: gen_lock_default_state
483-
assign lock_base[r] = '0;
484-
assign counter_base[r] = '0;
479+
assign lock_b[r] = '0;
480+
assign counter_b[r] = '0;
485481
end
486482

487483
// State Storage
488-
`FF(lock_q, lock_d, lock_base);
489-
`FF(counter_q, counter_d, counter_base);
484+
`FF(lock_q, lock_d, lock_b);
485+
`FF(counter_q, counter_d, counter_b);
490486

491487
///////////////////////////////////////////////////////////////////////////////////////////////////
492488
// Build error flag
@@ -497,19 +493,18 @@ module time_TMR_end # (
497493
// always have at least two data elements that are the same in the first 3 elements.
498494
// Make output only 1 for a signly cycle even if internal pipeline is stopped
499495

500-
logic fault_detected_d[REP], fault_detected_q[REP];
496+
logic [REP-1:0] fault_detected_b, fault_detected_d, fault_detected_q;
501497

502498
for (genvar r = 0; r < REP; r++) begin: gen_flag_next_state
503499
assign fault_detected_d[r] = ~|full_same[2:0] & valid_i;
504500
end
505501

506502
// Default state
507-
logic fault_detected_base[REP];
508503
for (genvar r = 0; r < REP; r++) begin: gen_flag_default_state
509-
assign fault_detected_base[r] = '0;
504+
assign fault_detected_b[r] = '0;
510505
end
511506

512-
`FF(fault_detected_q, fault_detected_d, fault_detected_base);
507+
`FF(fault_detected_q, fault_detected_d, fault_detected_b);
513508

514509
for (genvar r = 0; r < REP; r++) begin: gen_flag_output
515510
assign fault_detected_ov[r] = fault_detected_d[r] & !fault_detected_q[r];

‎rtl/time_redundancy/time_TMR_start.sv

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -60,18 +60,18 @@ module time_TMR_start # (
6060
input logic ready_i
6161
);
6262
// Redundant Output signals
63-
logic ready_ov[REP];
64-
logic valid_ov[REP];
63+
logic [REP-1:0] ready_ov;
64+
logic [REP-1:0] valid_ov;
6565

6666
// State machine TLDR
6767
// - counting the state from 0 to 2 if the handshake is good
6868
// - counting the ID up whenever the state goes back to 0
6969

7070
// Next State Combinatorial Logic
7171
typedef enum logic [1:0] {STORE_AND_SEND, SEND, REPLICATE_ONE, REPLICATE_TWO} state_t;
72-
state_t state_v[REP], state_d[REP], state_q[REP];
73-
DataType data_v[REP], data_d[REP], data_q[REP];
74-
logic [IDSize-1:0] id_v[REP], id_d[REP], id_q[REP];
72+
state_t [REP-1:0] state_b, state_v, state_d, state_q;
73+
DataType [REP-1:0] data_b, data_v, data_d, data_q;
74+
logic [REP-1:0][IDSize-1:0] id_b, id_v, id_d, id_q;
7575

7676
for (genvar r = 0; r < REP; r++) begin: gen_next_state
7777
always_comb begin : gen_next_state_comb
@@ -129,10 +129,6 @@ module time_TMR_start # (
129129
end
130130

131131
// Generate default cases
132-
state_t state_b[REP];
133-
DataType data_b[REP];
134-
logic [IDSize-1:0] id_b[REP];
135-
136132
for (genvar r = 0; r < REP; r++) begin: gen_default_state
137133
assign state_b[r] = STORE_AND_SEND;
138134
assign data_b[r] = 0;

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