refactor: migrate to common_cells v2

Author: ricted98

Bender.lock

@@ -1,14 +1,14 @@
 packages:
   apb:
-    revision: 77ddf073f194d44b9119949d2421be59789e69ae
-    version: 0.2.4
+    revision: c36e398b5e9b02f3a5fb1511be02764c94e1c413
+    version: null
     source:
       Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: a256a3b86394fedf19e361047fccfdd7f6ef83e4
-    version: 0.39.9
+    revision: a9c20696b43a86752365a47e32481e980e50a485
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -23,8 +23,8 @@ packages:
     dependencies:
     - common_cells
   common_cells:
-    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
-    version: 1.39.0
+    revision: eb6372fbd02028d239295b862423e3a60d5c0c75
+    version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:

Bender.yml

@@ -11,10 +11,10 @@ package:
     - "Paul Scheffler <paulsc@iis.ee.ethz.ch>"
 
 dependencies:
-  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0 }
-  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.0 }
+  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       rev: v2-test    }
+  axi:                 { git: "https://github.com/pulp-platform/axi.git",                rev: common-cells-v2 }
   axi_stream:          { git: "https://github.com/pulp-platform/axi_stream.git",         version: 0.1.1  }
-  apb:                 { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4  }
+  apb:                 { git: "https://github.com/pulp-platform/apb.git",                rev: common-cells-v2  }
 
 sources:
   files:

src/channel_allocator/slink_ch_alloc.sv

@@ -163,13 +163,12 @@ module slink_ch_alloc
   // auto-flushing) is already stalled. Without the synchronization FIFO, parts
   // of the late arriving packet would be accidently merged into the earlier partial
   // packet if it wasn't for this FIFO acting as the sync barrier.
-  stream_register #(
+  cc_stream_register #(
     .T            ( slice_payload_t   )
   ) i_rx_recv_barrier (
     .clk_i,
     .rst_ni,
     .clr_i      ( cfg_rx_clear_i           ),
-    .testmode_i ( 1'b0                     ),
     .data_i     ( s_rx_recv_barrier_payload_in     ),
     .valid_i    ( s_rx_recv_barrier_valid_in  ),
     .ready_o    ( s_rx_recv_barrier_ready_out ),
@@ -205,7 +204,7 @@ module slink_ch_alloc
 
   assign s_rx_despreader2slice_valid = |s_rx_despreader2slice_payload.valid;
 
-  spill_register #(
+  cc_spill_register #(
     .T(slice_payload_t),
     .Bypass(1'b0)
   ) i_rx_decoupling_slice (

src/channel_allocator/slink_stream_dechopper.sv

@@ -55,9 +55,9 @@ module slink_stream_dechopper #(
   assign s_out_buffer_clear = output_valid_q;
 
   // Count trailing 1s
-  lzc #(
+  cc_lzc #(
     .WIDTH(Width),
-    .MODE(0)
+    .MODE(cc_pkg::LZC_TRAILING_ZERO_CNT)
   ) i_lzc(
     .in_i(~valid_i),
     .cnt_o(s_chopsize),

src/slink.sv

@@ -222,7 +222,7 @@ module slink
     .cfg_flow_control_fifo_clear_i           ( cfg_flow_control_fifo_clear                      ),
     .cfg_raw_mode_en_i                       ( reg2hw.raw_mode_en.raw_mode_en.value ),
     .cfg_raw_mode_in_ch_sel_i                (
-      reg2hw.raw_mode_in_ch_sel.raw_mode_in_ch_sel.value[cf_math_pkg::idx_width(NumChannels)-1:0] ),
+      reg2hw.raw_mode_in_ch_sel.raw_mode_in_ch_sel.value[cc_pkg::idx_width(NumChannels)-1:0]    ),
     .cfg_raw_mode_in_data_o                  ( raw_mode_in_data_out ),
     .cfg_raw_mode_in_data_valid_o            ( raw_mode_in_data_valid                           ),
     .cfg_raw_mode_in_data_ready_i            (

src/slink_link_layer.sv

@@ -77,14 +77,13 @@ module slink_link_layer #(
   logic flow_control_fifo_valid_out, flow_control_fifo_ready_out;
   logic flow_control_fifo_valid_in, flow_control_fifo_ready_in;
 
-  stream_fifo #(
+  cc_stream_fifo #(
     .T(phy_data_chan_t),
     .DEPTH (RecvFifoDepth)
   ) i_flow_control_fifo (
     .clk_i      ( clk_i                         ),
     .rst_ni     ( rst_ni                        ),
     .flush_i    ( cfg_flow_control_fifo_clear_i ),
-    .testmode_i ( 1'b0                          ),
     .usage_o    (                               ),
     .data_i     ( data_in_i                     ),
     .valid_i    ( flow_control_fifo_valid_in    ),
@@ -95,13 +94,12 @@ module slink_link_layer #(
   );
 
   for (genvar i = 0; i < PayloadSplits; i++) begin : gen_recv_reg
-    stream_register #(
+    cc_stream_register #(
       .T (phy_data_chan_t)
     ) i_recv_reg (
       .clk_i      ( clk_i                       ),
       .rst_ni     ( rst_ni                      ),
       .clr_i      ( 1'b0                        ),
-      .testmode_i ( 1'b0                        ),
       .valid_i    ( recv_reg_in_valid[i]        ),
       .ready_o    ( recv_reg_in_ready[i]        ),
       .data_i     ( flow_control_fifo_data_out  ),
@@ -215,14 +213,13 @@ module slink_link_layer #(
     end
   end
 
-  fifo_v3 #(
+  cc_fifo #(
     .dtype  ( phy_data_t        ),
     .DEPTH  ( RawModeFifoDepth  )
   ) i_raw_mode_fifo (
     .clk_i      ( clk_i                                   ),
     .rst_ni     ( rst_ni                                  ),
     .flush_i    ( cfg_raw_mode_out_data_fifo_clear_i      ),
-    .testmode_i ( 1'b0                                    ),
     .full_o     ( raw_mode_fifo_full                      ),
     .empty_o    ( raw_mode_fifo_empty                     ),
     .usage_o    ( cfg_raw_mode_out_data_fifo_fill_state_o ),

src/slink_phys_layer.sv

@@ -134,7 +134,7 @@ module slink_phys_layer_rx #(
   //   CLOCK DOMAIN CROSSING   //
   ///////////////////////////////
 
-  cdc_fifo_gray #(
+  cc_cdc_fifo_gray #(
     .T            ( phy_data_t                        ),
     .LOG_DEPTH    ( $clog2(FifoDepth) + CdcSyncStages ),
     .SYNC_STAGES  ( CdcSyncStages                     )

src/slink_prot_layer.sv

@@ -219,14 +219,13 @@ module slink_prot_layer #(
   assign axis_out_req_o.t.data = axis_reg_data_out;
   assign axis_reg_ready_out = axis_out_rsp_i.tready;
 
-  stream_fifo #(
+  cc_stream_fifo #(
     .DEPTH  ( 2           ),
     .T      (  payload_t  )
   ) i_axis_out_reg (
     .clk_i      ( clk_i               ),
     .rst_ni     ( rst_ni              ),
     .flush_i    ( 1'b0                ),
-    .testmode_i ( 1'b0                ),
     .usage_o    (                     ),
     .valid_i    ( axis_reg_valid_in   ),
     .ready_o    ( axis_reg_ready_in   ),