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bowwang
committed
[hw] add support for vlxblk
1 parent 6983a65 commit c6a1746

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6 files changed

+306
-39
lines changed

6 files changed

+306
-39
lines changed

‎hw/ip/snitch/src/snitch.sv‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2063,8 +2063,9 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
20632063
end
20642064
`endif
20652065
// FP Sequencer
2066-
FREP_O,
2067-
FREP_I: begin
2066+
// FREP_O,
2067+
// FREP_I: begin
2068+
FREP_O: begin
20682069
if (FP_EN) begin
20692070
opa_select = Reg;
20702071
write_rd = 1'b0;
@@ -2553,7 +2554,18 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
25532554
riscv_instr::VLUXEI8_V,
25542555
riscv_instr::VLUXEI16_V,
25552556
riscv_instr::VLUXEI32_V,
2556-
riscv_instr::VLUXEI64_V: begin
2557+
riscv_instr::VLUXEI64_V,
2558+
riscv_instr::VLUXEI64_V,
2559+
riscv_instr::VLXBLK4EI8_V,
2560+
riscv_instr::VLXBLK4EI16_V,
2561+
riscv_instr::VLXBLK6EI8_V,
2562+
riscv_instr::VLXBLK6EI16_V,
2563+
riscv_instr::VLXBLK8EI8_V,
2564+
riscv_instr::VLXBLK8EI16_V,
2565+
riscv_instr::VLXBLK12EI8_V,
2566+
riscv_instr::VLXBLK12EI16_V,
2567+
riscv_instr::VLXBLK16EI8_V,
2568+
riscv_instr::VLXBLK16EI16_V: begin
25572569
if (RVV) begin
25582570
write_rd = 1'b0;
25592571
uses_rd = 1'b0;

‎hw/ip/spatz/src/rvv_pkg.sv‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,14 @@ package rvv_pkg;
1717
EW_64 = 3'b011
1818
} vew_e;
1919

20+
typedef enum logic [2:0] {
21+
BLKLEN_4 = 3'd0,
22+
BLKLEN_6 = 3'd1,
23+
BLKLEN_8 = 3'd2,
24+
BLKLEN_12 = 3'd3,
25+
BLKLEN_16 = 3'd4
26+
} vlblklen_e;
27+
2028
typedef enum logic [2:0] {
2129
LMUL_RES = 3'b100,
2230
LMUL_F8 = 3'b101,
@@ -51,4 +59,5 @@ package rvv_pkg;
5159
OPCFG = 3'b111
5260
} opcodev_func3_e;
5361

62+
5463
endpackage : rvv_pkg

‎hw/ip/spatz/src/spatz_decoder.sv‎

Lines changed: 86 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -89,12 +89,11 @@ module spatz_decoder
8989
automatic vreg_t ls_vd = decoder_req_i.instr[11:7];
9090
automatic vreg_t ls_rs1 = decoder_req_i.instr[19:15];
9191
automatic vreg_t ls_s2 = decoder_req_i.instr[24:20];
92-
automatic logic [2:0] ls_width = decoder_req_i.instr[14:12];
92+
automatic logic [2:0] ls_width = decoder_req_i.instr[14:12];//index ew
9393
automatic logic ls_vm = decoder_req_i.instr[25];
9494
automatic logic [1:0] ls_mop = decoder_req_i.instr[27:26];
9595
automatic logic ls_mew = decoder_req_i.instr[28];
9696
automatic logic [2:0] ls_nf = decoder_req_i.instr[31:29];
97-
9897
// Retrieve VSEW
9998
unique case ({ls_mew, ls_width})
10099
4'b0000: spatz_req.vtype.vsew = EW_8;
@@ -103,7 +102,6 @@ module spatz_decoder
103102
4'b0111: spatz_req.vtype.vsew = EW_64;
104103
default: illegal_instr = 1'b1;
105104
endcase
106-
107105
spatz_req.op_mem.vm = ls_vm;
108106
spatz_req.ex_unit = LSU;
109107

@@ -156,7 +154,38 @@ module spatz_decoder
156154
spatz_req.op_mem.ew = spatz_req.vtype.vsew;
157155
spatz_req.vtype.vsew = decoder_req_i.vtype.vsew;
158156
end
159-
157+
// riscv_instr::VLXBLK4EI8_V,
158+
// riscv_instr::VLXBLK4EI16_V,
159+
// riscv_instr::VLXBLK6EI8_V,
160+
// riscv_instr::VLXBLK6EI16_V,
161+
// riscv_instr::VLXBLK8EI8_V,
162+
// riscv_instr::VLXBLK8EI16_V,
163+
// riscv_instr::VLXBLK12EI8_V,
164+
// riscv_instr::VLXBLK12EI16_V,
165+
// riscv_instr::VLXBLK16EI8_V,
166+
// riscv_instr::VLXBLK16EI16_V: begin
167+
// spatz_req.op = VLXBLK;
168+
// spatz_req.op_mem.is_load = 1'b1;
169+
// spatz_req.vd = ls_vd;
170+
// spatz_req.use_vd = 1'b1;
171+
// spatz_req.rs1 = decoder_req_i.rs1;
172+
// spatz_req.vs2 = ls_s2;
173+
// spatz_req.use_vs2 = 1'b1;
174+
175+
// unique case (ls_nf)
176+
// 3'd0: spatz_req.op_mem.blk_len = BLKLEN_4;
177+
// 3'd1: spatz_req.op_mem.blk_len = BLKLEN_6;
178+
// 3'd2: spatz_req.op_mem.blk_len = BLKLEN_8;
179+
// 3'd3: spatz_req.op_mem.blk_len = BLKLEN_12;
180+
// 3'd4: spatz_req.op_mem.blk_len = BLKLEN_16;
181+
// default: illegal_instr = 1'b1;
182+
// endcase
183+
184+
// // Indexed block load: op_mem.ew = index width, vtype.vsew = data element width
185+
// spatz_req.op_mem.ew = spatz_req.vtype.vsew;
186+
// spatz_req.vtype.vsew = decoder_req_i.vtype.vsew;
187+
188+
// end
160189
riscv_instr::VSE8_V,
161190
riscv_instr::VSE16_V,
162191
riscv_instr::VSE32_V,
@@ -209,6 +238,59 @@ module spatz_decoder
209238
endcase // decoder_req_i.instr
210239
end
211240

241+
riscv_instr::VLXBLK4EI8_V,
242+
riscv_instr::VLXBLK4EI16_V,
243+
riscv_instr::VLXBLK6EI8_V,
244+
riscv_instr::VLXBLK6EI16_V,
245+
riscv_instr::VLXBLK8EI8_V,
246+
riscv_instr::VLXBLK8EI16_V,
247+
riscv_instr::VLXBLK12EI8_V,
248+
riscv_instr::VLXBLK12EI16_V,
249+
riscv_instr::VLXBLK16EI8_V,
250+
riscv_instr::VLXBLK16EI16_V: begin
251+
automatic vreg_t blk_vd = decoder_req_i.instr[11:7];
252+
automatic vreg_t blk_rs1 = decoder_req_i.instr[19:15];
253+
automatic vreg_t blk_vs2 = decoder_req_i.instr[24:20];
254+
automatic logic [2:0] blk_width = decoder_req_i.instr[14:12];
255+
automatic logic [6:0] blk_funct7 = decoder_req_i.instr[31:25];
256+
257+
spatz_req.op = VLXBLK;
258+
spatz_req.ex_unit = LSU;
259+
spatz_req.op_mem.is_load = 1'b1;
260+
261+
spatz_req.vd = blk_vd;
262+
spatz_req.use_vd = 1'b1;
263+
264+
spatz_req.rs1 = decoder_req_i.rs1;
265+
266+
spatz_req.vs2 = blk_vs2;
267+
spatz_req.use_vs2 = 1'b1;
268+
269+
// New custom encoding has no vm field. Treat as unmasked.
270+
spatz_req.op_mem.vm = 1'b1;
271+
272+
// Indexed block load:
273+
// op_mem.ew = index element width
274+
// vtype.vsew = data element width from current vtype CSR
275+
unique case (blk_width)
276+
3'b000: spatz_req.op_mem.ew = EW_8;
277+
3'b101: spatz_req.op_mem.ew = EW_16;
278+
default: illegal_instr = 1'b1;
279+
endcase
280+
281+
spatz_req.vtype.vsew = decoder_req_i.vtype.vsew;
282+
283+
// Block length is encoded in funct7[31:25]
284+
unique case (blk_funct7)
285+
7'b0001000: spatz_req.op_mem.blk_len = BLKLEN_4;
286+
7'b0001001: spatz_req.op_mem.blk_len = BLKLEN_6;
287+
7'b0001010: spatz_req.op_mem.blk_len = BLKLEN_8;
288+
7'b0001011: spatz_req.op_mem.blk_len = BLKLEN_12;
289+
7'b0001100: spatz_req.op_mem.blk_len = BLKLEN_16;
290+
default: illegal_instr = 1'b1;
291+
endcase
292+
end
293+
212294
// Vector instruction
213295
riscv_instr::VADD_VV,
214296
riscv_instr::VADD_VX,

‎hw/ip/spatz/src/spatz_fpu_sequencer.sv‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -586,7 +586,9 @@ module spatz_fpu_sequencer
586586
{riscv_instr::VLE8_V, riscv_instr::VLE16_V, riscv_instr::VLE32_V, riscv_instr::VLE64_V,
587587
riscv_instr::VLSE8_V, riscv_instr::VLSE16_V, riscv_instr::VLSE32_V, riscv_instr::VLSE64_V,
588588
riscv_instr::VLOXEI8_V, riscv_instr::VLOXEI16_V, riscv_instr::VLOXEI32_V, riscv_instr::VLOXEI64_V,
589-
riscv_instr::VLUXEI8_V, riscv_instr::VLUXEI16_V, riscv_instr::VLUXEI32_V, riscv_instr::VLUXEI64_V};
589+
riscv_instr::VLUXEI8_V, riscv_instr::VLUXEI16_V, riscv_instr::VLUXEI32_V, riscv_instr::VLUXEI64_V,
590+
riscv_instr::VLXBLK8EI8_V
591+
};
590592

591593
// Is the current instruction a vector store?
592594
logic is_vector_store;

‎hw/ip/spatz/src/spatz_pkg.sv.tpl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ package spatz_pkg;
141141
// Slide instructions
142142
VSLIDEUP, VSLIDEDOWN,
143143
// Load instructions
144-
VLE, VLSE, VLXE,
144+
VLE, VLSE, VLXE, VLXBLK,
145145
// Store instructions
146146
VSE, VSSE, VSXE,
147147
// Config instruction
@@ -202,6 +202,7 @@ package spatz_pkg;
202202
logic vm;
203203
logic is_load;
204204
vew_e ew;
205+
logic [2:0] blk_len; // block length encoding
205206
} op_mem_t;
206207

207208
typedef struct packed {

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