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SmephiteNavaneeth-KunhiPurayil
Smephite
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Navaneeth-KunhiPurayil
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hw: Add SystemRDL for Spatz cluster generation
Note: This only adds the RDL files, but does not yet generate the register files.
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‎hw/system/spatz_cluster/src/spatz_cluster.rdl.tpl‎

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## Copyright 2025 ETH Zurich and University of Bologna.
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## Solderpad Hardware License, Version 0.51, see LICENSE for details.
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## SPDX-License-Identifier: SHL-0.51
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// Copyright 2025 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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${disclaimer}
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<%!
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import math
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def next_power_of_2(n):
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"""Returns the next power of 2 greater than or equal to n."""
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return 1 if n == 0 else 2**math.ceil(math.log2(n))
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%>
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`ifndef __${cfg['name'].upper()}_RDL__
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`define __${cfg['name'].upper()}_RDL__
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`include "spatz_cluster_peripheral_reg.rdl"
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addrmap ${cfg['name']} {
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default regwidth = ${cfg['dma_data_width']};
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mem tcdm {
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mementries = ${hex(int(cfg['tcdm']['size'] * 1024 * 8 / cfg['dma_data_width']))};
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memwidth = ${cfg['dma_data_width']};
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};
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mem bootrom {
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mementries = ${hex(int(4 * 1024 * 8 / cfg['dma_data_width']))};
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memwidth = ${cfg['dma_data_width']};
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};
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external tcdm tcdm ;
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external bootrom bootrom @ ${hex(next_power_of_2(cfg['tcdm']['size']) * 1024)};
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spatz_cluster_peripheral_reg peripheral_reg @ ${hex((next_power_of_2(cfg['tcdm']['size'])+4) * 1024)};
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};
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`endif // __${cfg['name'].upper()}_RDL__

‎hw/system/spatz_cluster/src/spatz_cluster_peripheral/spatz_cluster_peripheral_reg.rdl‎

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// Copyright 2025 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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`ifndef __SPATZ_CLUSTER_PERIPHERAL_REG_RDL__
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`define __SPATZ_CLUSTER_PERIPHERAL_REG_RDL__
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addrmap spatz_cluster_peripheral_reg #(
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longint unsigned NumPerfCounters = 2
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) {
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default regwidth = 64;
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reg perf_cnt_en {
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field {
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name = "enable";
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desc = "Enable a particular performance counter to start tracking.";
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hw = r;
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sw = rw;
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} enable[0:0] = 1;
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};
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enum perf_metric {
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cycle = 0 {
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desc = "Cycle counter. Counts up as long as the cluster is powered.";
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};
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tcdm_accessed = 1 {
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desc = "Increased whenever the TCDM is accessed. Each individual access is tracked,
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so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
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so it doesn't matter whether the cores or for example the SSR hardware accesses
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the TCDM. _This is a cluster-global signal._";
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};
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tcdm_congested = 2 {
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desc = "Incremented whenever an access towards the TCDM is made but the arbitration
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logic didn't grant the access (due to congestion). It's strictly less than tcdm_accessed.
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_This is a cluster-global signal._";
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};
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issue_fpu = 3 {
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desc = "Operations performed in the FPU. Includes both operations initiated by the
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sequencer and by the core. When the Xfrep extension is available, this counter is
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equivalent to issue_fpu_seq (see description of issue_fpu_seq). If the Xfrep extension
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is not supported, then it is equivalent to issue_core_to_fpu. _This is a hart-local signal._";
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};
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issue_fpu_seq = 4 {
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desc = "Incremented whenever the FPU Sequencer issues an FPU instruction.
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Might not be available if the hardware doesn't support FREP.
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Note that all FP instructions offloaded by the core to the FPU are routed
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through the sequencer (although not necessarily buffered) and thus are also counted.
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The instructions issued independently by the FPU sequencer could thus be
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calculated as issue_fpu_seq_proper = issue_fpu_seq - issue_core_to_fpu.
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_This is a hart-local signal._";
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};
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issue_core_to_fpu = 5 {
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desc = "Incremented whenever the core issues an FPU instruction.
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_This is a hart-local signal._";
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};
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retired_instr = 6 {
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desc = "Instructions retired by the core, both offloaded and not. Does not
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count instructions issued independently by the FPU sequencer.
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_This is a hart-local signal._";
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};
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retired_load = 7 {
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desc = "Load instructions retired by the core. _This is a hart-local signal._";
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};
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retired_i = 8 {
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desc = "Base instructions retired by the core. _This is a hart-local signal._";
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};
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retired_acc = 9 {
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desc = "Offloaded instructions retired by the core. _This is a hart-local signal._";
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};
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dma_aw_stall = 10 {
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desc = "Incremented whenever aw_valid = 1 but aw_ready = 0.
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_This is a DMA-local signal_";
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};
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dma_ar_stall = 11 {
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desc = "Incremented whenever ar_valid = 1 but ar_ready = 0.
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_This is a DMA-local signal_";
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};
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dma_r_stall = 12 {
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desc = "Incremented whenever r_ready = 1 but r_valid = 0.
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_This is a DMA-local signal_";
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};
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dma_w_stall = 13 {
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desc = "Incremented whenever w_valid = 1 but w_ready = 0.
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_This is a DMA-local signal_";
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};
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dma_buf_w_stall = 14 {
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desc = "Incremented whenever w_ready = 1 but w_valid = 0.
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_This is a DMA-local signal_";
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};
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dma_buf_r_stall = 15 {
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desc = "Incremented whenever r_valid = 1 but r_ready = 0.
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_This is a DMA-local signal_";
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};
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dma_aw_done = 16 {
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desc = "Incremented whenever AW handshake occurs.
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_This is a DMA-local signal_";
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};
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dma_aw_bw = 17 {
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desc = "Whenever AW handshake occurs, the counter is incremented
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by the number of bytes transfered for this transaction
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_This is a DMA-local signal_";
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};
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dma_ar_done = 18 {
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desc = "Incremented whenever AR handshake occurs.
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_This is a DMA-local signal_";
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};
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dma_ar_bw = 19 {
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desc = "Whenever AR handshake occurs, the counter is incremented
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by the number of bytes transfered for this transaction
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_This is a DMA-local signal_";
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};
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dma_r_done = 20 {
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desc = "Incremented whenever R handshake occurs.
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_This is a DMA-local signal_";
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};
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dma_r_bw = 21 {
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desc = "Whenever R handshake occurs, the counter is incremented
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by the number of bytes transfered in this cycle
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_This is a DMA-local signal_";
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};
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dma_w_done = 22 {
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desc = "Incremented whenvever W handshake occurs.
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_This is a DMA-local signal_";
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};
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dma_w_bw = 23 {
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desc = "Whenever W handshake occurs, the counter is incremented
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by the number of bytes transfered in this cycle
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_This is a DMA-local signal_";
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};
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dma_b_done = 24 {
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desc = "Incremented whenever B handshake occurs.
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_This is a DMA-local signal_";
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};
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dma_busy = 25 {
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desc = "Incremented whenever DMA is busy.
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_This is a DMA-local signal_";
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};
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icache_miss = 26 {
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desc = "Incremented for instruction cache misses.
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_This is a hart-local signal_";
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};
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icache_hit = 27 {
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desc = "Incremented for instruction cache hits.
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_This is a hart-local signal_";
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};
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icache_prefetch = 28 {
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desc = "Incremented for instruction cache prefetches.
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_This is a hart-local signal_";
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};
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icache_double_hit = 29 {
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desc = "Incremented for instruction cache double hit.
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_This is a hart-local signal_";
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};
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icache_stall = 30 {
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desc = "Incremented for instruction cache stalls.
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_This is a hart-local signal_";
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};
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};
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reg perf_cnt_sel {
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desc = "Select the metric that is tracked for each performance counter.";
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field {
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name = "hart";
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desc = "Select from which hart in the cluster, starting from `0`,
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the event should be counted. For each performance counter
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the cores can be selected individually. If a hart greater
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than the cluster's total hart size is selected the selection
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will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
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will be selected.";
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hw = rw;
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sw = rw;
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} hart[9:0];
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};
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reg perf_cnt {
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desc = "Performance counter. Set corresponding perf_cnt_sel register depending on what
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performance metric and hart you would like to track.";
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field {
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desc = "Performance counter";
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hw = rw;
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sw = rw;
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onwrite = wclr;
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} perf_counter[47:0];
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};
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reg cl_clint_set {
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desc = "Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
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of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.";
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field {
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desc = "Set cluster-local interrupt of hart i";
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sw = w;
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hw = r;
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} cl_clint_set[31:0];
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};
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reg cl_clint_clear {
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desc = "Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
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of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.";
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field {
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desc = "Set cluster-local interrupt of hart i";
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sw = w;
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hw = r;
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} cl_clint_clear[31:0];
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};
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reg hw_barrier {
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desc = "Hardware barrier register. Loads to this register will block until all cores have
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performed the load. At this stage we know that they reached the same point in the control flow,
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i.e., the cores are synchronized.";
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field {
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desc = "Hardware barrier register.";
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sw = r;
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hw = rw;
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} hw_barrier[31:0];
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};
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reg icache_prefetch_enable {
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desc = "Controls prefetching of the instruction cache.";
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field {
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desc = "Enable instruction prefetching.";
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hw = r;
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sw = w;
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} icache_prefetch_enable[0:0] = 1;
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};
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reg spatz_status {
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desc = "Sets the status of the Spatz cluster.";
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field {
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desc = "Indicates the cluster is computing a kernel.";
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sw = w;
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hw = r;
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} hw_barrier[0:0] = 0;
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};
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reg cluster_boot_control {
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desc = "Controls the cluster boot process";
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field {
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desc = "Post-bootstrapping entry point.";
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sw = rw;
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hw = r;
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} boot_cluster[31:0] = 0;
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};
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reg cluster_eoc_exit {
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desc = "End of computation and exit status register";
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field {
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desc = "Indicates the end of computation and exit status.";
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sw = rw;
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hw = r;
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} eoc_exit[31:0] = 0;
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};
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// Required for PeakRDL to define the `perf_metric` enum in
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// the generated RTL file, as this seems not to be done for
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// for registers defined to be `external`.
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reg unused {
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desc = "Unused register added to print enum";
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field {
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sw=r; hw=na;
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encode = perf_metric;
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} f[4:0] = 0;
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};
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regfile perf_regs {
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perf_cnt_en perf_cnt_en[NumPerfCounters];
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external perf_cnt_sel perf_cnt_sel[NumPerfCounters];
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external perf_cnt perf_cnt[NumPerfCounters];
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};
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perf_regs perf_regs;
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external cl_clint_set cl_clint_set;
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external cl_clint_clear cl_clint_clear;
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external hw_barrier hw_barrier;
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icache_prefetch_enable icache_prefetch_enable;
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spatz_status spatz_status;
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cluster_boot_control cluster_boot_control;
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cluster_eoc_exit cluster_eoc_exit;
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unused unused;
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};
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`endif // __SPATZ_CLUSTER_PERIPHERAL_REG_RDL__

‎util/clustergen.py‎

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with open(outdir / "spatz_cluster_wrapper.sv", "w") as f:
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f.write(cluster_tb.render_wrapper())
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with open(outdir / "spatz_cluster.rdl", "w") as f:
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f.write(cluster_tb.render_rdl())
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with open(outdir / "link.ld", "w") as f:
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f.write(cluster_tb.render_linker_script())
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‎util/clustergen/cluster.py‎

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@@ -157,6 +157,7 @@ class SnitchCluster(Generator):
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files = {
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"spatzpkg": "src/spatz_pkg.sv.tpl",
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"wrapper": "src/spatz_cluster_wrapper.sv.tpl",
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"rdl": "src/spatz_cluster.rdl.tpl",
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"testbench": "tb/testbench.sv.tpl",
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}
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@@ -184,6 +185,13 @@ def l1_region(self):
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"""Return L1 Region as tuple. Base and length."""
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return (self.cfg["cluster_base_addr"], self.cfg["tcdm"]["size"])
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def render_rdl(self):
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"""Render the cluster RDL"""
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cfg_template = self.templates.get_template(self.files["rdl"])
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return cfg_template.render_unicode(
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cfg=self.cfg, to_sv_hex=to_sv_hex, disclaimer=self.DISCLAIMER
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)
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def render_wrapper(self):
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"""Render the cluster wrapper"""
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cfg_template = self.templates.get_template(self.files["wrapper"])
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# Store Snitch cluster config in separate variable
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self.cluster = SnitchCluster(cfg["cluster"], pma_cfg)
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def render_rdl(self):
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return self.cluster.render_rdl()
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def render_wrapper(self):
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return self.cluster.render_wrapper()
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