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2 | 2 |
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3 | 3 | #include "am1808.h" |
4 | 4 |
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| 5 | +// Shared RAM (control input) |
| 6 | +typedef struct shared_ram { |
| 7 | + // Declare this as a u32 to force more-efficient codegen |
| 8 | + uint32_t pwms; |
| 9 | +} shared_ram; |
| 10 | +// XXX: The real address in use here is 0x80010000 |
| 11 | +// There appears to be a compiler bug where ctable entries with the MSB set |
| 12 | +// do not get optimized correctly. We lie to the PRU compiler here, but the |
| 13 | +// hardware indeed contains the correct address we *actually* want. |
| 14 | +static volatile shared_ram * const SHARED = (volatile shared_ram *)0x7f010000; |
| 15 | +#pragma ctable_entry 30 0x7f010000 |
| 16 | + |
| 17 | +// LED definitions PRU1_R30[n] |
| 18 | +#define LED0 12 |
| 19 | +#define LED1 10 |
| 20 | +#define LED2 13 |
| 21 | +#define LED3 11 |
| 22 | + |
| 23 | +static inline void update_pwm(uint8_t val, uint8_t time_now, uint32_t gpio_bit) { |
| 24 | + // We want to force generation of the optimized set/clr opcodes |
| 25 | + if (time_now < val) { |
| 26 | + asm volatile("set r30, r30, %0"::"I"(gpio_bit)); |
| 27 | + } else { |
| 28 | + asm volatile("clr r30, r30, %0"::"I"(gpio_bit)); |
| 29 | + } |
| 30 | +} |
| 31 | + |
5 | 32 | void main() { |
6 | | - __halt(); |
| 33 | + uint32_t pwms = 0; |
| 34 | + while (1) { |
| 35 | + // 24 MHz / 256 ==> 93.75 kHz tick rate for this counter |
| 36 | + uint8_t time_now = (*TIMER0_TIM34) >> 8; |
| 37 | + |
| 38 | + if (time_now == 0) { |
| 39 | + // 24 MHz / 256 / 256 ~= 366 Hz update rate |
| 40 | + pwms = SHARED->pwms; |
| 41 | + } |
| 42 | + |
| 43 | + update_pwm(pwms >> 0, time_now, LED0); |
| 44 | + update_pwm(pwms >> 8, time_now, LED1); |
| 45 | + update_pwm(pwms >> 16, time_now, LED2); |
| 46 | + update_pwm(pwms >> 24, time_now, LED3); |
| 47 | + } |
7 | 48 | } |
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