Trigger a host CPU interrupt on I2C transaction completion

Author: ArcaneNibble

am1808.h

@@ -65,6 +65,9 @@
 // 30 = Shared RAM                  0x80nnnn00
 // 31 = mDDR/DDR2 Data              0xC0nnnn00
 
+extern volatile __regio_symbol unsigned int __R30;
+extern volatile __regio_symbol unsigned int __R31;
+
 // Timer0 peripheral (only what we need)
 static volatile uint32_t * const TIMER0_TIM34 = (volatile uint32_t *)0x01C20014;
 

main.c

@@ -48,6 +48,13 @@ static inline void update_pwm(uint8_t val, uint8_t time_now, uint32_t gpio_bit)
 #define SENSOR_PORT_4_PIN_SCL   1
 #define SENSOR_PORT_4_PIN_SDA   (15 + 16)
 
+// I2C event definition. This currently is set up by the SUART code
+// and is thus defined to coexist with it.
+#define SENSOR_PORT_1_IRQ_EVT   42
+#define SENSOR_PORT_2_IRQ_EVT   44
+#define SENSOR_PORT_3_IRQ_EVT   46
+#define SENSOR_PORT_4_IRQ_EVT   48
+
 // This timeout specifies the *total permissible delay* of an I2C transaction.
 // This is the permissible sum total of all clock stretching as well as
 // the initial wait for the bus to become free. Time spent actually transferring
@@ -163,6 +170,10 @@ typedef struct i2c_state_struct {
     // Bit index of the IO pins in GPIO bank 0/1
     uint8_t scl_bit;
     uint8_t sda_bit;
+
+    // Event to trigger to inform the ARM of completion
+    // (has bit5 already set)
+    uint8_t intr_event;
 } i2c_state_struct;
 i2c_state_struct i2c_states[PBDRV_RPROC_EV3_PRU1_NUM_I2C_CHANNELS];
 
@@ -382,6 +393,7 @@ static void handle_i2c(volatile pbdrv_rproc_ev3_pru1_i2c_command_t *cmd, i2c_sta
                         0,
                         PBDRV_RPROC_EV3_PRU1_I2C_STAT_DONE | PBDRV_RPROC_EV3_PRU1_I2C_STAT_OK
                     );
+                    __R31 = i2c->intr_event;
                 }
             }
             break;
@@ -492,6 +504,7 @@ static void handle_i2c(volatile pbdrv_rproc_ev3_pru1_i2c_command_t *cmd, i2c_sta
             PBDRV_RPROC_EV3_PRU1_I2C_STAT_DONE | PBDRV_RPROC_EV3_PRU1_I2C_STAT_NAK
         );
         state = I2C_STATE_IDLE;
+        __R31 = i2c->intr_event;
     }
 
     if (0) {
@@ -505,6 +518,7 @@ static void handle_i2c(volatile pbdrv_rproc_ev3_pru1_i2c_command_t *cmd, i2c_sta
                 PBDRV_RPROC_EV3_PRU1_I2C_STAT_DONE | PBDRV_RPROC_EV3_PRU1_I2C_STAT_TIMEOUT
             );
             state = I2C_STATE_IDLE;
+            __R31 = i2c->intr_event;
         }
     }
 
@@ -521,12 +535,16 @@ void main() {
     // We initialize this in code to avoid having to copy a data ram binary
     i2c_states[0].scl_bit = SENSOR_PORT_1_PIN_SCL;
     i2c_states[0].sda_bit = SENSOR_PORT_1_PIN_SDA;
+    i2c_states[0].intr_event = SENSOR_PORT_1_IRQ_EVT;
     i2c_states[1].scl_bit = SENSOR_PORT_2_PIN_SCL;
     i2c_states[1].sda_bit = SENSOR_PORT_2_PIN_SDA;
+    i2c_states[1].intr_event = SENSOR_PORT_2_IRQ_EVT;
     i2c_states[2].scl_bit = SENSOR_PORT_3_PIN_SCL;
     i2c_states[2].sda_bit = SENSOR_PORT_3_PIN_SDA;
+    i2c_states[2].intr_event = SENSOR_PORT_3_IRQ_EVT;
     i2c_states[3].scl_bit = SENSOR_PORT_4_PIN_SCL;
     i2c_states[3].sda_bit = SENSOR_PORT_4_PIN_SDA;
+    i2c_states[3].intr_event = SENSOR_PORT_4_IRQ_EVT;
 
     while (1) {
         // 24 MHz / 256 ==> 93.75 kHz tick rate for this counter