@@ -46,7 +46,6 @@ class DebugSequenceCommonFunctions(DebugSequenceFunctionsDelegate):
4646
4747 def __init__ (self ) -> None :
4848 self ._ap_cache : Dict [APAddressBase , MEM_AP ] = {}
49- self ._transfer_error_ignored = False
5049
5150 @property
5251 def target (self ) -> CoreSightTarget :
@@ -144,16 +143,8 @@ def _get_dp(self, ignore_apid: bool = False) -> DebugPort:
144143
145144 def _get_ignore_errors (self ) -> bool :
146145 """@brief Whether the debug sequence has set __errorcontrol to ignore faults."""
147- errcontrol = self .context .get_variable ('__errorcontrol' ) & 1
148- if errcontrol :
149- self ._transfer_error_ignored = True
150- return errcontrol
151-
152- def _handle_ignore_errors (self ) -> None :
153- """@brief Clear sticky error bits if transfer errors were ignored."""
154- if self ._transfer_error_ignored :
155- self ._get_dp ().clear_sticky_err ()
156- self ._transfer_error_ignored = False
146+ errcontrol = self .context .get_variable ('__errorcontrol' )
147+ return (errcontrol & 1 ) == 1
157148
158149 def sequence (self , name : str ) -> None :
159150 # This call will raise if the named sequence is invalid. However, we should have already
@@ -179,7 +170,6 @@ def sequence(self, name: str) -> None:
179170
180171 def read8 (self , addr : int ) -> int :
181172 try :
182- self ._handle_ignore_errors ()
183173 return self ._get_mem_ap ().read8 (addr )
184174 except exceptions .TransferError as err :
185175 if self ._get_ignore_errors ():
@@ -190,7 +180,6 @@ def read8(self, addr: int) -> int:
190180
191181 def read16 (self , addr : int ) -> int :
192182 try :
193- self ._handle_ignore_errors ()
194183 return self ._get_mem_ap ().read16 (addr )
195184 except exceptions .TransferError as err :
196185 if self ._get_ignore_errors ():
@@ -201,7 +190,6 @@ def read16(self, addr: int) -> int:
201190
202191 def read32 (self , addr : int ) -> int :
203192 try :
204- self ._handle_ignore_errors ()
205193 return self ._get_mem_ap ().read32 (addr )
206194 except exceptions .TransferError as err :
207195 if self ._get_ignore_errors ():
@@ -212,7 +200,6 @@ def read32(self, addr: int) -> int:
212200
213201 def read64 (self , addr : int ) -> int :
214202 try :
215- self ._handle_ignore_errors ()
216203 return self ._get_mem_ap ().read64 (addr )
217204 except exceptions .TransferError as err :
218205 if self ._get_ignore_errors ():
@@ -223,7 +210,6 @@ def read64(self, addr: int) -> int:
223210
224211 def readap (self , addr : int ) -> int :
225212 try :
226- self ._handle_ignore_errors ()
227213 ap_addr = self ._get_ap_addr ()
228214 reg_addr = ap_addr .address | addr
229215 return self ._get_dp ().read_ap (reg_addr )
@@ -236,7 +222,6 @@ def readap(self, addr: int) -> int:
236222
237223 def readaccessap (self , addr : int ) -> int :
238224 try :
239- self ._handle_ignore_errors ()
240225 dp = self ._get_dp (True )
241226 apacc = dp .apacc_memory_interface
242227 return apacc .read32 (addr )
@@ -249,7 +234,6 @@ def readaccessap(self, addr: int) -> int:
249234
250235 def readdp (self , addr : int ) -> int :
251236 try :
252- self ._handle_ignore_errors ()
253237 return self ._get_dp (True ).read_dp (addr )
254238 except exceptions .TransferError as err :
255239 if self ._get_ignore_errors ():
@@ -260,7 +244,6 @@ def readdp(self, addr: int) -> int:
260244
261245 def write8 (self , addr : int , val : int ) -> None :
262246 try :
263- self ._handle_ignore_errors ()
264247 self ._get_mem_ap ().write8 (addr , val )
265248 self .target .flush ()
266249 except exceptions .TransferError as err :
@@ -271,7 +254,6 @@ def write8(self, addr: int, val: int) -> None:
271254
272255 def write16 (self , addr : int , val : int ) -> None :
273256 try :
274- self ._handle_ignore_errors ()
275257 self ._get_mem_ap ().write16 (addr , val )
276258 self .target .flush ()
277259 except exceptions .TransferError as err :
@@ -282,7 +264,6 @@ def write16(self, addr: int, val: int) -> None:
282264
283265 def write32 (self , addr : int , val : int ) -> None :
284266 try :
285- self ._handle_ignore_errors ()
286267 self ._get_mem_ap ().write32 (addr , val )
287268 self .target .flush ()
288269 except exceptions .TransferError as err :
@@ -293,7 +274,6 @@ def write32(self, addr: int, val: int) -> None:
293274
294275 def write64 (self , addr : int , val : int ) -> None :
295276 try :
296- self ._handle_ignore_errors ()
297277 self ._get_mem_ap ().write64 (addr , val )
298278 self .target .flush ()
299279 except exceptions .TransferError as err :
@@ -304,7 +284,6 @@ def write64(self, addr: int, val: int) -> None:
304284
305285 def writeap (self , addr : int , val : int ) -> None :
306286 try :
307- self ._handle_ignore_errors ()
308287 ap_addr = self ._get_ap_addr ()
309288 reg_addr = ap_addr .address | addr
310289 self ._get_dp ().write_ap (reg_addr , val )
@@ -317,7 +296,6 @@ def writeap(self, addr: int, val: int) -> None:
317296
318297 def writeaccessap (self , addr : int , val : int ) -> None :
319298 try :
320- self ._handle_ignore_errors ()
321299 dp = self ._get_dp (True )
322300 apacc = dp .apacc_memory_interface
323301 apacc .write32 (addr , val )
@@ -330,7 +308,6 @@ def writeaccessap(self, addr: int, val: int) -> None:
330308
331309 def writedp (self , addr : int , val : int ) -> None :
332310 try :
333- self ._handle_ignore_errors ()
334311 self ._get_dp (True ).write_dp (addr , val )
335312 self .target .flush ()
336313 except exceptions .TransferError as err :
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