Commit 3d7f47b
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[rl] Add XPU support to GRPO training pipeline
Enable the full GRPO RL pipeline (trainer + vLLM generator) to run on
Intel XPU alongside CUDA with minimal, config-driven changes.
Key changes:
1. Device detection via ZE_AFFINITY_MASK (always present on Intel GPU
systems) -- no runtime torch.xpu.is_available() checks needed.
2. expandable_segments guard: PYTORCH_CUDA_ALLOC_CONF is only set when
ZE_AFFINITY_MASK is absent. On XPU the CUDA allocator config corrupts
oneDNN USM pointers, causing oneCCL collective failures.
3. Bootstrap callable in PerHostProvisioner sets ZE_AFFINITY_MASK (XPU)
or CUDA_VISIBLE_DEVICES (CUDA) inside the child process before Level
Zero / CUDA runtime initialization.
4. Generator attention_config field using vLLM's AttentionConfig type.
Default (None) preserves existing behavior; XPU config passes
AttentionConfig() to let vLLM's platform auto-select the backend.
5. decoder.py: gate separate_full_blocks kwarg on inspect.signature for
PyTorch version compatibility.
6. XPU config in config_registry.py: disable max_autotune (avoids
OUT_OF_RESOURCES on backward), override FlexAttention class var.
7. Remove xpu_compat.py monkey-patching in favor of the above.
Files changed:
- torchtitan/models/common/decoder.py (version compat, no behavior change)
- torchtitan/experiments/rl/__init__.py (ZE_AFFINITY_MASK guard, lazy imports)
- torchtitan/experiments/rl/train.py (bootstrap callable, XPU guards)
- torchtitan/experiments/rl/actors/generator.py (attention_config field)
- torchtitan/experiments/rl/actors/trainer.py (remove apply_patches)
- torchtitan/experiments/rl/examples/alphabet_sort/config_registry.py (XPU config)
Verified: 10-step GRPO on 4x Intel Max 1550, reward 0.194 -> 0.351.1 parent 31948fb commit 3d7f47b
6 files changed
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File tree
- torchtitan
- experiments/rl
- actors
- examples/alphabet_sort
- models/common
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