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[xen] Update to latest stable release headers
Update to the headers from the latest Xen stable release, and mark all imported headers as permitted for UEFI Secure Boot. Signed-off-by: Michael Brown <mcb30@ipxe.org>
1 parent 8e31ac9 commit f1bcd16

20 files changed

Lines changed: 545 additions & 81 deletions

‎src/include/ipxe/nonxen.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,9 @@
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1010
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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12+
/* Provide stub definitions if no platform-specific header exists */
13+
#ifndef XEN_GUEST_HANDLE
14+
1215
#define __XEN_GUEST_HANDLE(name) __guest_handle_ ## name
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1417
#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
@@ -32,6 +35,8 @@ struct arch_shared_info {};
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3336
#define XEN_LEGACY_MAX_VCPUS 0
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38+
#endif
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3540
struct xen_hypervisor;
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3742
static inline __attribute__ (( always_inline )) unsigned long

‎src/include/xen/arch-arm.h‎

Lines changed: 82 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#define __XEN_PUBLIC_ARCH_ARM_H__
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1313
FILE_LICENCE ( MIT );
14+
FILE_SECBOOT ( PERMITTED );
1415

1516
/*
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* `incontents 50 arm_abi Hypercall Calling Convention
@@ -106,6 +107,7 @@ FILE_LICENCE ( MIT );
106107
* Exactly these sub-operations are supported:
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* * HVMOP_set_param
108109
* * HVMOP_get_param
110+
* * HVMOP_guest_request_vm_event
109111
*
110112
* HYPERVISOR_grant_table_op
111113
* All generic sub-operations
@@ -118,6 +120,32 @@ FILE_LICENCE ( MIT );
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* HYPERVISOR_argo_op
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* All generic sub-operations
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*
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* HYPERVISOR_hypfs_op
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* All generic sub-operations
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*
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* HYPERVISOR_platform_op
127+
* Exactly these sub-operations are supported:
128+
* * XENPF_settime64
129+
*
130+
* HYPERVISOR_vm_assist
131+
* All generic sub-operations
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*
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* HYPERVISOR_dm_op
134+
* Exactly these sub-operations are supported:
135+
* * XEN_DMOP_create_ioreq_server
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* * XEN_DMOP_get_ioreq_server_info
137+
* * XEN_DMOP_map_io_range_to_ioreq_server
138+
* * XEN_DMOP_unmap_io_range_from_ioreq_server
139+
* * XEN_DMOP_set_ioreq_server_state
140+
* * XEN_DMOP_destroy_ioreq_server
141+
* * XEN_DMOP_set_irq_level
142+
* * XEN_DMOP_nr_vcpus
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*
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* HYPERVISOR_xsm_op
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* All generic sub-operations
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*
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* HYPERVISOR_multicall
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*
121149
* Other notes on the ARM ABI:
122150
*
123151
* - struct start_info is not exported to ARM guests.
@@ -154,8 +182,10 @@ FILE_LICENCE ( MIT );
154182

155183
#define XEN_HYPERCALL_TAG 0XEA1
156184

157-
#define int64_aligned_t int64_t __attribute__((aligned(8)))
158-
#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
185+
#if defined(__XEN__) || defined(__XEN_TOOLS__) || defined(__GNUC__)
186+
#define int64_aligned_t int64_t __attribute__((__aligned__(8)))
187+
#define uint64_aligned_t uint64_t __attribute__((__aligned__(8)))
188+
#endif
159189

160190
#ifndef __ASSEMBLY__
161191
#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
@@ -182,7 +212,7 @@ FILE_LICENCE ( MIT );
182212
do { \
183213
__typeof__(&(hnd)) _sxghr_tmp = &(hnd); \
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_sxghr_tmp->q = 0; \
185-
_sxghr_tmp->p = val; \
215+
_sxghr_tmp->p = (val); \
186216
} while ( 0 )
187217
#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
188218

@@ -298,10 +328,16 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
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299329
#define XEN_DOMCTL_CONFIG_TEE_NONE 0
300330
#define XEN_DOMCTL_CONFIG_TEE_OPTEE 1
331+
#define XEN_DOMCTL_CONFIG_TEE_FFA 2
332+
333+
#define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0
334+
#define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1
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302336
struct xen_arch_domainconfig {
303337
/* IN/OUT */
304338
uint8_t gic_version;
339+
/* IN - Contains SVE vector length divided by 128 */
340+
uint8_t sve_vl;
305341
/* IN */
306342
uint16_t tee_type;
307343
/* IN */
@@ -320,6 +356,8 @@ struct xen_arch_domainconfig {
320356
*
321357
*/
322358
uint32_t clock_frequency;
359+
/* IN */
360+
uint8_t arm_sci_type;
323361
};
324362
#endif /* __XEN__ || __XEN_TOOLS__ */
325363

@@ -338,36 +376,36 @@ typedef uint64_t xen_callback_t;
338376

339377
/* PSR bits (CPSR, SPSR) */
340378

341-
#define PSR_THUMB (1<<5) /* Thumb Mode enable */
342-
#define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */
343-
#define PSR_IRQ_MASK (1<<7) /* Interrupt mask */
344-
#define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */
345-
#define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */
346-
#define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */
347-
#define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
348-
#define PSR_JAZELLE (1<<24) /* Jazelle Mode */
349-
#define PSR_Z (1<<30) /* Zero condition flag */
379+
#define PSR_THUMB (1U <<5) /* Thumb Mode enable */
380+
#define PSR_FIQ_MASK (1U <<6) /* Fast Interrupt mask */
381+
#define PSR_IRQ_MASK (1U <<7) /* Interrupt mask */
382+
#define PSR_ABT_MASK (1U <<8) /* Asynchronous Abort mask */
383+
#define PSR_BIG_ENDIAN (1U << 9) /* arm32: Big Endian Mode */
384+
#define PSR_DBG_MASK (1U << 9) /* arm64: Debug Exception mask */
385+
#define PSR_IT_MASK (0x0600fc00U) /* Thumb If-Then Mask */
386+
#define PSR_JAZELLE (1U << 24) /* Jazelle Mode */
387+
#define PSR_Z (1U << 30) /* Zero condition flag */
350388

351389
/* 32 bit modes */
352-
#define PSR_MODE_USR 0x10
353-
#define PSR_MODE_FIQ 0x11
354-
#define PSR_MODE_IRQ 0x12
355-
#define PSR_MODE_SVC 0x13
356-
#define PSR_MODE_MON 0x16
357-
#define PSR_MODE_ABT 0x17
358-
#define PSR_MODE_HYP 0x1a
359-
#define PSR_MODE_UND 0x1b
360-
#define PSR_MODE_SYS 0x1f
390+
#define PSR_MODE_USR 0x10U
391+
#define PSR_MODE_FIQ 0x11U
392+
#define PSR_MODE_IRQ 0x12U
393+
#define PSR_MODE_SVC 0x13U
394+
#define PSR_MODE_MON 0x16U
395+
#define PSR_MODE_ABT 0x17U
396+
#define PSR_MODE_HYP 0x1aU
397+
#define PSR_MODE_UND 0x1bU
398+
#define PSR_MODE_SYS 0x1fU
361399

362400
/* 64 bit modes */
363-
#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
364-
#define PSR_MODE_EL3h 0x0d
365-
#define PSR_MODE_EL3t 0x0c
366-
#define PSR_MODE_EL2h 0x09
367-
#define PSR_MODE_EL2t 0x08
368-
#define PSR_MODE_EL1h 0x05
369-
#define PSR_MODE_EL1t 0x04
370-
#define PSR_MODE_EL0t 0x00
401+
#define PSR_MODE_BIT 0x10U /* Set iff AArch32 */
402+
#define PSR_MODE_EL3h 0x0dU
403+
#define PSR_MODE_EL3t 0x0cU
404+
#define PSR_MODE_EL2h 0x09U
405+
#define PSR_MODE_EL2t 0x08U
406+
#define PSR_MODE_EL1h 0x05U
407+
#define PSR_MODE_EL1t 0x04U
408+
#define PSR_MODE_EL0t 0x00U
371409

372410
/*
373411
* We set PSR_Z to be able to boot Linux kernel versions with an invalid
@@ -457,7 +495,7 @@ typedef uint64_t xen_callback_t;
457495
#define GUEST_RAM0_SIZE xen_mk_ullong(0xc0000000)
458496

459497
/* 4GB @ 4GB Prefetch Memory for VPCI */
460-
#define GUEST_VPCI_ADDR_TYPE_PREFETCH_MEM xen_mk_ullong(0x42000000)
498+
#define GUEST_VPCI_ADDR_TYPE_PREFETCH_MEM xen_mk_ullong(0x43000000)
461499
#define GUEST_VPCI_PREFETCH_MEM_ADDR xen_mk_ullong(0x100000000)
462500
#define GUEST_VPCI_PREFETCH_MEM_SIZE xen_mk_ullong(0x100000000)
463501

@@ -475,6 +513,7 @@ typedef uint64_t xen_callback_t;
475513
#define GUEST_MAX_VCPUS 128
476514

477515
/* Interrupts */
516+
478517
#define GUEST_TIMER_VIRT_PPI 27
479518
#define GUEST_TIMER_PHYS_S_PPI 29
480519
#define GUEST_TIMER_PHYS_NS_PPI 30
@@ -485,6 +524,19 @@ typedef uint64_t xen_callback_t;
485524
#define GUEST_VIRTIO_MMIO_SPI_FIRST 33
486525
#define GUEST_VIRTIO_MMIO_SPI_LAST 43
487526

527+
/*
528+
* SGI is the preferred delivery mechanism of FF-A pending notifications or
529+
* schedule recveive interrupt. SGIs 8-15 are normally not used by a guest
530+
* as they in a non-virtualized system typically are assigned to the secure
531+
* world. Here we're free to use SGI 8-15 since they are virtual and have
532+
* nothing to do with the secure world.
533+
*
534+
* For partitioning of SGIs see also Arm Base System Architecture v1.0C,
535+
* https://developer.arm.com/documentation/den0094/
536+
*/
537+
#define GUEST_FFA_NOTIF_PEND_INTR_ID 8
538+
#define GUEST_FFA_SCHEDULE_RECV_INTR_ID 9
539+
488540
/* PSCI functions */
489541
#define PSCI_cpu_suspend 0
490542
#define PSCI_cpu_off 1

‎src/include/xen/arch-ppc.h‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2+
/*
3+
* Copyright (C) IBM Corp. 2005, 2006
4+
* Copyright (C) Raptor Engineering, LLC 2023
5+
*
6+
* Authors: Hollis Blanchard <hollisb@us.ibm.com>
7+
* Timothy Pearson <tpearson@raptorengineering.com>
8+
* Shawn Anastasio <sanastasio@raptorengineering.com>
9+
*/
10+
11+
#ifndef __XEN_PUBLIC_ARCH_PPC_H__
12+
#define __XEN_PUBLIC_ARCH_PPC_H__
13+
14+
FILE_LICENCE ( MIT );
15+
FILE_SECBOOT ( PERMITTED );
16+
17+
#if defined(__XEN__) || defined(__XEN_TOOLS__)
18+
#define int64_aligned_t int64_t __attribute__((__aligned__(8)))
19+
#define uint64_aligned_t uint64_t __attribute__((__aligned__(8)))
20+
#endif
21+
22+
#ifndef __ASSEMBLY__
23+
#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
24+
typedef union { type *p; unsigned long q; } \
25+
__guest_handle_ ## name; \
26+
typedef union { type *p; uint64_aligned_t q; } \
27+
__guest_handle_64_ ## name
28+
29+
#define __DEFINE_XEN_GUEST_HANDLE(name, type) \
30+
___DEFINE_XEN_GUEST_HANDLE(name, type); \
31+
___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
32+
#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
33+
#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name
34+
#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
35+
#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name
36+
#define set_xen_guest_handle_raw(hnd, val) \
37+
do { \
38+
__typeof__(&(hnd)) sxghr_tmp_ = &(hnd); \
39+
sxghr_tmp_->q = 0; \
40+
sxghr_tmp_->p = (val); \
41+
} while ( 0 )
42+
#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
43+
44+
#ifdef __XEN_TOOLS__
45+
#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0)
46+
#endif
47+
48+
typedef uint64_t xen_pfn_t;
49+
#define PRI_xen_pfn PRIx64
50+
#define PRIu_xen_pfn PRIu64
51+
52+
/*
53+
* Maximum number of virtual CPUs in legacy multi-processor guests.
54+
* Only one. All other VCPUS must use VCPUOP_register_vcpu_info.
55+
*/
56+
#define XEN_LEGACY_MAX_VCPUS 1
57+
58+
typedef uint64_t xen_ulong_t;
59+
#define PRI_xen_ulong PRIx64
60+
61+
/*
62+
* User-accessible registers: most of these need to be saved/restored
63+
* for every nested Xen invocation.
64+
*/
65+
struct vcpu_guest_core_regs
66+
{
67+
uint64_t gprs[32];
68+
uint64_t lr;
69+
uint64_t ctr;
70+
uint64_t srr0;
71+
uint64_t srr1;
72+
uint64_t pc;
73+
uint64_t msr;
74+
uint64_t fpscr; /* XXX Is this necessary */
75+
uint64_t xer;
76+
uint64_t hid4; /* debug only */
77+
uint64_t dar; /* debug only */
78+
uint32_t dsisr; /* debug only */
79+
uint32_t cr;
80+
uint32_t __pad; /* good spot for another 32bit reg */
81+
uint32_t entry_vector;
82+
};
83+
typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
84+
85+
typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */ /* XXX timebase */
86+
87+
/* ONLY used to communicate with dom0! See also struct exec_domain. */
88+
struct vcpu_guest_context {
89+
vcpu_guest_core_regs_t user_regs; /* User-level CPU registers */
90+
uint64_t sdr1; /* Pagetable base */
91+
/* XXX etc */
92+
};
93+
typedef struct vcpu_guest_context vcpu_guest_context_t;
94+
DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
95+
96+
struct arch_shared_info {
97+
uint64_t boot_timebase;
98+
};
99+
100+
struct arch_vcpu_info {
101+
};
102+
103+
struct xen_arch_domainconfig {
104+
};
105+
106+
typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t;
107+
108+
#endif /* !__ASSEMBLY__ */
109+
110+
#endif /* __XEN_PUBLIC_ARCH_PPC_H__ */

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