Skip to content

Commit 97d952b

Browse files
author
Rouven Spreckels
committed
Maintain.
1 parent 795fdbf commit 97d952b

18 files changed

Lines changed: 92 additions & 204 deletions

File tree

‎Cargo.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[package]
22
name = "lav"
3-
version = "0.8.3"
3+
version = "0.8.4"
44
edition = "2024"
55
authors = ["Rouven Spreckels <rs@qu1x.dev>"]
66
description = "Lane-Associated Vector (LAV): Portable SIMD vector trait as GAT of SIMD lane trait."

‎RELEASES.md‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
# Version 0.8.4 (2026-02-14)
2+
3+
* Synchronize with nightly Rust.
4+
* Update KaTeX.
5+
16
# Version 0.8.3 (2025-12-06)
27

38
* Fix KaTeX.

‎katex.html‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11

22

33
<!-- KaTeX -->
4-
<link rel="stylesheet" href="https://cdn.jsdelivr.net/npm/katex@0.16.25/dist/katex.min.css"
5-
integrity="sha384-WcoG4HRXMzYzfCgiyfrySxx90XSl2rxY5mnVY5TwtWE6KLrArNKn0T/mOgNL0Mmi" crossorigin="anonymous">
6-
<script src="https://cdn.jsdelivr.net/npm/katex@0.16.25/dist/katex.min.js"
7-
integrity="sha384-J+9dG2KMoiR9hqcFao0IBLwxt6zpcyN68IgwzsCSkbreXUjmNVRhPFTssqdSGjwQ" crossorigin="anonymous"></script>
8-
<script src="https://cdn.jsdelivr.net/npm/katex@0.16.25/dist/contrib/auto-render.min.js"
4+
<link rel="stylesheet" href="https://cdn.jsdelivr.net/npm/katex@0.16.28/dist/katex.min.css"
5+
integrity="sha384-Wsr4Nh3yrvMf2KCebJchRJoVo1gTU6kcP05uRSh5NV3sj9+a8IomuJoQzf3sMq4T" crossorigin="anonymous">
6+
<script src="https://cdn.jsdelivr.net/npm/katex@0.16.28/dist/katex.min.js"
7+
integrity="sha384-+W9OcrYK2/bD7BmUAk+xeFAyKp0QjyRQUCxeU31dfyTt/FrPsUgaBTLLkVf33qWt" crossorigin="anonymous"></script>
8+
<script src="https://cdn.jsdelivr.net/npm/katex@0.16.28/dist/contrib/auto-render.min.js"
99
integrity="sha384-hCXGrW6PitJEwbkoStFjeJxv+fSOOQKOPbJxSfM6G5sWZjAyWhXiTIIAmQqnlLlh" crossorigin="anonymous"></script>
1010
<script>
1111
let tex = function() {

‎src/bits/mod.rs‎

Lines changed: 6 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
@@ -11,7 +11,7 @@ use core::{
1111
ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Rem, RemAssign, Sub, SubAssign},
1212
ops::{BitAnd, BitAndAssign, BitOr, BitOrAssign, BitXor, BitXorAssign, Not},
1313
ops::{Shl, ShlAssign, Shr, ShrAssign},
14-
simd::{LaneCount, SimdElement, SupportedLaneCount},
14+
simd::SimdElement,
1515
};
1616

1717
mod u32;
@@ -52,9 +52,7 @@ where
5252
Self: SimdElement,
5353
{
5454
/// Associated vector.
55-
type Simd<const N: usize>: SimdBits<Self, N>
56-
where
57-
LaneCount<N>: SupportedLaneCount;
55+
type Simd<const N: usize>: SimdBits<Self, N>;
5856

5957
/// The smallest value that can be represented by this integer type.
6058
const MIN: Self;
@@ -83,10 +81,7 @@ where
8381
/// Constructs a SIMD vector by setting all lanes to the given value.
8482
#[must_use]
8583
#[inline]
86-
fn splat<const N: usize>(self) -> Self::Simd<N>
87-
where
88-
LaneCount<N>: SupportedLaneCount,
89-
{
84+
fn splat<const N: usize>(self) -> Self::Simd<N> {
9085
Self::Simd::splat(self)
9186
}
9287

@@ -108,10 +103,7 @@ where
108103
/// Panic if the size of the SIMD vector is different from `N` times that of the scalar.
109104
#[must_use]
110105
#[inline]
111-
fn as_simd<const N: usize>(slice: &[Self]) -> (&[Self], &[Self::Simd<N>], &[Self])
112-
where
113-
LaneCount<N>: SupportedLaneCount,
114-
{
106+
fn as_simd<const N: usize>(slice: &[Self]) -> (&[Self], &[Self::Simd<N>], &[Self]) {
115107
Self::Simd::as_simd(slice)
116108
}
117109

@@ -138,10 +130,7 @@ where
138130
#[inline]
139131
fn as_simd_mut<const N: usize>(
140132
slice: &mut [Self],
141-
) -> (&mut [Self], &mut [Self::Simd<N>], &mut [Self])
142-
where
143-
LaneCount<N>: SupportedLaneCount,
144-
{
133+
) -> (&mut [Self], &mut [Self::Simd<N>], &mut [Self]) {
145134
Self::Simd::as_simd_mut(slice)
146135
}
147136
}

‎src/bits/u32.rs‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,13 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
55

66
use super::Bits;
7-
use core::simd::{LaneCount, Simd, SupportedLaneCount};
7+
use core::simd::Simd;
88

99
impl Bits for u32 {
10-
type Simd<const N: usize>
11-
= Simd<Self, N>
12-
where
13-
LaneCount<N>: SupportedLaneCount;
10+
type Simd<const N: usize> = Simd<Self, N>;
1411

1512
const MIN: Self = Self::MIN;
1613
const MAX: Self = Self::MAX;

‎src/bits/u64.rs‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,13 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
55

66
use super::Bits;
7-
use core::simd::{LaneCount, Simd, SupportedLaneCount};
7+
use core::simd::Simd;
88

99
impl Bits for u64 {
10-
type Simd<const N: usize>
11-
= Simd<Self, N>
12-
where
13-
LaneCount<N>: SupportedLaneCount;
10+
type Simd<const N: usize> = Simd<Self, N>;
1411

1512
const MIN: Self = Self::MIN;
1613
const MAX: Self = Self::MAX;

‎src/real/f32.rs‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,17 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
55

66
use super::Real;
7-
use core::{
8-
cmp::Ordering,
9-
num::FpCategory,
10-
simd::{LaneCount, Simd, SupportedLaneCount},
11-
};
7+
use core::{cmp::Ordering, num::FpCategory, simd::Simd};
128

139
#[cfg(feature = "target-features")]
1410
use target_features::CURRENT_TARGET;
1511

1612
impl Real for f32 {
1713
type Bits = u32;
18-
type Simd<const N: usize>
19-
= Simd<Self, N>
20-
where
21-
LaneCount<N>: SupportedLaneCount;
14+
type Simd<const N: usize> = Simd<Self, N>;
2215

2316
#[cfg(feature = "target-features")]
2417
const NATIVE_LANE_COUNT: usize = match CURRENT_TARGET.suggested_simd_width::<Self>() {

‎src/real/f64.rs‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,17 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
55

66
use super::Real;
7-
use core::{
8-
cmp::Ordering,
9-
num::FpCategory,
10-
simd::{LaneCount, Simd, SupportedLaneCount},
11-
};
7+
use core::{cmp::Ordering, num::FpCategory, simd::Simd};
128

139
#[cfg(feature = "target-features")]
1410
use target_features::CURRENT_TARGET;
1511

1612
impl Real for f64 {
1713
type Bits = u64;
18-
type Simd<const N: usize>
19-
= Simd<Self, N>
20-
where
21-
LaneCount<N>: SupportedLaneCount;
14+
type Simd<const N: usize> = Simd<Self, N>;
2215

2316
#[cfg(feature = "target-features")]
2417
const NATIVE_LANE_COUNT: usize = match CURRENT_TARGET.suggested_simd_width::<Self>() {

‎src/real/mod.rs‎

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use core::{
1313
iter::{Product, Sum},
1414
num::{FpCategory, ParseFloatError},
1515
ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Rem, RemAssign, Sub, SubAssign},
16-
simd::{LaneCount, SimdElement, SupportedLaneCount},
16+
simd::SimdElement,
1717
str::FromStr,
1818
};
1919

@@ -54,9 +54,7 @@ where
5454
/// Associated bits representation.
5555
type Bits: Bits;
5656
/// Associated vector.
57-
type Simd<const N: usize>: SimdReal<Self, N>
58-
where
59-
LaneCount<N>: SupportedLaneCount;
57+
type Simd<const N: usize>: SimdReal<Self, N>;
6058

6159
/// Native lane count of current build target or `1` if unknown.
6260
#[cfg(feature = "target-features")]
@@ -444,10 +442,7 @@ where
444442
/// Constructs a SIMD vector by setting all lanes to the given value.
445443
#[must_use]
446444
#[inline]
447-
fn splat<const N: usize>(self) -> Self::Simd<N>
448-
where
449-
LaneCount<N>: SupportedLaneCount,
450-
{
445+
fn splat<const N: usize>(self) -> Self::Simd<N> {
451446
Self::Simd::splat(self)
452447
}
453448

@@ -469,10 +464,7 @@ where
469464
/// Panic if the size of the SIMD vector is different from `N` times that of the scalar.
470465
#[must_use]
471466
#[inline]
472-
fn as_simd<const N: usize>(slice: &[Self]) -> (&[Self], &[Self::Simd<N>], &[Self])
473-
where
474-
LaneCount<N>: SupportedLaneCount,
475-
{
467+
fn as_simd<const N: usize>(slice: &[Self]) -> (&[Self], &[Self::Simd<N>], &[Self]) {
476468
Self::Simd::as_simd(slice)
477469
}
478470

@@ -499,10 +491,7 @@ where
499491
#[inline]
500492
fn as_simd_mut<const N: usize>(
501493
slice: &mut [Self],
502-
) -> (&mut [Self], &mut [Self::Simd<N>], &mut [Self])
503-
where
504-
LaneCount<N>: SupportedLaneCount,
505-
{
494+
) -> (&mut [Self], &mut [Self::Simd<N>], &mut [Self]) {
506495
Self::Simd::as_simd_mut(slice)
507496
}
508497
}

‎src/simd_bits/mod.rs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// Copyright © 2021-2025 Rouven Spreckels <rs@qu1x.dev>
1+
// Copyright © 2021-2026 Rouven Spreckels <rs@qu1x.dev>
22
//
33
// This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of
44
// the MPL was not distributed with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
@@ -12,7 +12,7 @@ use core::{
1212
ops::{BitAnd, BitAndAssign, BitOr, BitOrAssign, BitXor, BitXorAssign, Not},
1313
ops::{Index, IndexMut},
1414
ops::{Shl, ShlAssign, Shr, ShrAssign},
15-
simd::{LaneCount, Simd, SupportedLaneCount},
15+
simd::Simd,
1616
};
1717

1818
mod u32;
@@ -24,7 +24,6 @@ mod u64;
2424
#[allow(clippy::len_without_is_empty)]
2525
pub trait SimdBits<B: Bits, const N: usize>
2626
where
27-
LaneCount<N>: SupportedLaneCount,
2827
Self: Send + Sync + Clone + Copy + Default,
2928
Self: PartialEq + Eq + PartialOrd + Ord,
3029
Self: From<Simd<B, N>> + Into<Simd<B, N>>,

0 commit comments

Comments
 (0)