rasm2 (arm64): Fails to assemble instructions it can correctly disassemble (MSUB, STR)

[Mrqqeat]

Environment

# r2 -v
radare2 6.0.4 1 @ windows-x86-64
birth: git.6.0.4 Sat 09/27/2025__18:14:24.90
commit: 54b6f9b5056fd8e0ce7a5fc3651fc2abf1960194
options: gpl -O? cs:5 cl:1 meson

Description

The rasm2 assembler for the ARM64 architecture exhibits a round-trip failure for specific instructions. It can successfully disassemble certain machine code sequences, but when attempting to assemble the exact same mnemonic syntax, it returns an error.

This has been observed with an MSUB (Multiply-Subtract) instruction and an STR (Store Register) instruction using a valid immediate offset.

The expected behavior is that rasm2 should successfully assemble these instructions, producing the original machine code.

Steps to Reproduce

Here are two test cases that demonstrate the bug.

Test Case 1: MSUB Instruction

Disassembly works as expected, correctly identifying the instruction.

# rasm2 -d -a arm -b 64 "0795099b"
msub x7, x8, x9, x5

However, assembling the output from the disassembler fails.

# rasm2 -a arm -b 64 "msub x7, x8, x9, x5"
ERROR: Cannot assemble 'msub x7, x8, x9, x5' at line 1

---

Test Case 2: STR Instruction with Immediate Offset

Similarly, disassembly of an STR instruction with a valid, scaled immediate offset works correctly.

# rasm2 -d -a arm -b 64 "022e10f9"
str x2, [x16, 0x2058]

But assembling the same instruction fails.

# rasm2 -a arm -b 64 "str x2, [x16, 0x2058]"
ERROR: Cannot assemble 'str x2, [x16, 0x2058]' at line 1

Analysis of Failures

It is important to note that these two failures likely stem from different root causes:

1. The STR failure appears to be directly related to the bug reported in rasm2 (arm64): Fails to assemble valid LDR instructions with specific immediate offsets #24520. The offset 0x2058 is a valid multiple of 8, and the failure pattern is identical to the one observed with LDR instructions. This suggests a systemic issue in how the assembler parses or validates scaled immediate offsets for load/store operations.

2. The MSUB failure, on the other hand, seems to be a distinct and separate issue. This is a data-processing instruction that does not use immediate offset addressing. Its failure to assemble points to a different problem, likely within the assembler's logic for parsing this specific instruction mnemonic or its register operands.