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raquentinraquentin
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setup nix flake (poorly) (#40)
* mct * lift clash sources to root * update nix * ragequit nix * non-cabal nix works * base flake, downgrade clash 1.8.1, new ci * devShell -> devShells * retry ci * fixed fr * add clash-ghc * get ci off nix * cabal bs * remove --enable-tests * move cd * remove haskell ci
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‎.github/workflows/ci.yml

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- name: Run Simulation
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run: |
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cd hdl/sv/moving_average_accumulator
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cd cores/moving_average_accumulator
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make test
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‎hdl/sv/moving_average_accumulator/Makefile ‎cores/moving_average_accumulator/Makefile

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‎hdl/sv/moving_average_accumulator/moving_average_accumulator.sv ‎cores/moving_average_accumulator/moving_average_accumulator.sv

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‎hdl/sv/moving_average_accumulator/tb.cpp ‎cores/moving_average_accumulator/tb.cpp

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‎cores/pipelined_order_book/README.md

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<!-- omit in toc -->
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# Simple Nix Starter Project
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This starter project contains the scaffolding needed to integrate Clash with the Nix Stack build system. Read [Simple Starter Project](https://github.com/clash-lang/clash-starters/blob/main/simple/README.md) for more information on the various files.
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<!-- omit in toc -->
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# Table of Contents
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- [Getting this project](#getting-this-project)
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- [Building and testing this project](#building-and-testing-this-project)
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- [REPL](#repl)
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- [Adding custom dependencies / updating nix](#adding-custom-dependencies--updating-nix)
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# Getting this project
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Run `nix-shell --packages stack --run "stack new my-clash-project clash-lang/simple-nix"`.
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# Building and testing this project
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Build the project with:
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```bash
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nix-build
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```
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Verilog code will be available under the `result/share/verilog` directory.
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Modify the `hdl` variable in `default.nix` to configure whether to generate
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SystemVerilog or VHDL.
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However development itself is more streamlined by using a Nix shell. Start one
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by invoking:
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```
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nix-shell
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```
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Then, to run the tests defined in `tests/`:
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```bash
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cabal run test-library
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cabal run doctests
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```
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To compile the project to VHDL run:
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```bash
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cabal run clash -- Example.Project --vhdl
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```
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You can find the HDL files in `vhdl/`. The source can be found in `src/Example/Project.hs`.
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# REPL
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Clash offers a [REPL](https://en.wikipedia.org/wiki/Read%E2%80%93eval%E2%80%93print_loop) as a quick way to try things, similar to Python's `python` or Ruby's `irb`. Open the REPL by invoking:
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```
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cabal run clashi
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```
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# Adding custom dependencies / updating nix
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`niv` is available after opening `nix-shell`. See [niv on Hackage](https://hackage.haskell.org/package/niv) for more information.

‎hdl/haskell/src/bin/Clash.hs ‎cores/pipelined_order_book/bin/Clash.hs

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‎hdl/haskell/src/bin/Clashi.hs ‎cores/pipelined_order_book/bin/Clashi.hs

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‎hdl/haskell/src/cabal.project ‎cores/pipelined_order_book/cabal.project

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packages:
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punt-engine-haskell-cores.cabal
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pipelined-order-book.cabal
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write-ghc-environment-files: always
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‎cores/pipelined_order_book/hie.yaml

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cradle:
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cabal:
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- path: "./src"
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component: "lib:pipelined-order-book"
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- path: "./tests/doctests.hs"
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component: "pipelined-order-book:doctests"
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- path: "./tests"
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component: "pipelined-order-book:test-library"
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- path: "./bin/Clashi.hs"
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component: "pipelined-order-book:exe:clashi"
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- path: "./bin/Clash.hs"
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component: "pipelined-order-book:exe:clash"

‎hdl/haskell/src/punt-engine-haskell-cores.cabal ‎cores/pipelined_order_book/pipelined-order-book.cabal

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cabal-version: 2.4
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name: punt-engine-haskell-cores
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name: pipelined-order-book
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version: 0.1
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license: MIT
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license: GPL-3.0-only
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author: Race Williams <[email protected]>
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maintainer: Race Williams <[email protected]>
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Cabal,
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-- clash-prelude will set suitable version bounds for the plugins
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-- TODO: get to work with 1.8.2
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clash-prelude >= 1.8.1 && < 1.10,
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ghc-typelits-natnormalise,
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ghc-typelits-extra,
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import: common-options
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hs-source-dirs: src
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exposed-modules:
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FixParser.Top
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Example.Project
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default-language: Haskell2010
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-- Builds the executable 'clash', with punt-engine-haskell-cores project in scope
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-- Builds the executable 'clash', with pipelined-order-book project in scope
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executable clash
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main-is: bin/Clash.hs
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default-language: Haskell2010
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Build-Depends: base, clash-ghc, punt-engine-haskell-cores
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if !os(Windows)
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ghc-options: -dynamic
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Build-Depends: base, clash-ghc, pipelined-order-book
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-- Builds the executable 'clashi', with punt-engine-haskell-cores project in scope
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-- Builds the executable 'clashi', with pipelined-order-book project in scope
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executable clashi
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main-is: bin/Clashi.hs
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default-language: Haskell2010
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if !os(Windows)
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ghc-options: -dynamic
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build-depends: base, clash-ghc, punt-engine-haskell-cores
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build-depends: base, clash-ghc, pipelined-order-book
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test-suite doctests
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type: exitcode-stdio-1.0
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hs-source-dirs: tests
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build-depends:
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base,
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punt-engine-haskell-cores,
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pipelined-order-book,
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doctest-parallel >= 0.2 && < 0.4,
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test-suite test-library
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other-modules:
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Tests.Example.Project
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build-depends:
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punt-engine-haskell-cores,
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pipelined-order-book,
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QuickCheck,
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clash-prelude-hedgehog,
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hedgehog,
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tasty >= 1.2 && < 1.5,
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tasty >= 1.2 && < 1.6,
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tasty-hedgehog,
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tasty-th

‎hdl/haskell/src/src/Example/Project.hs ‎cores/pipelined_order_book/src/Example/Project.hs

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‎hdl/haskell/src/tests/Tests/Example/Project.hs ‎cores/pipelined_order_book/tests/Tests/Example/Project.hs

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‎hdl/haskell/src/tests/doctests.hs ‎cores/pipelined_order_book/tests/doctests.hs

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import Test.DocTest (mainFromCabal)
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main :: IO ()
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main = mainFromCabal "punt-engine-haskell-cores" =<< getArgs
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main = mainFromCabal "my-clash-project" =<< getArgs
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‎hdl/haskell/src/tests/unittests.hs ‎cores/pipelined_order_book/tests/unittests.hs

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‎cores/pipelined_order_book/verilog/Example.Project.topEntity/accum.sdc

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create_clock -name {CLK} -period 20.000 -waveform {0.000 10.000} [get_ports {CLK}]
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‎cores/pipelined_order_book/verilog/Example.Project.topEntity/accum.v

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/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
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** GENERATED BY CLASH 1.8.1. DO NOT MODIFY.
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*/
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`default_nettype none
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`timescale 100fs/100fs
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module accum
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( // Inputs
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input wire CLK // clock
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, input wire RST // reset
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, input wire EN // enable
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, input wire [7:0] DIN
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// Outputs
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, output wire [7:0] DOUT
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);
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reg [7:0] s = 8'd0;
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// register begin
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always @(posedge CLK or posedge RST) begin : s_register
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if ( RST) begin
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s <= 8'd0;
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end else if (EN) begin
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s <= (s + DIN);
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end
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end
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// register end
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assign DOUT = s;
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endmodule
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‎cores/pipelined_order_book/verilog/Example.Project.topEntity/accum_shim.cpp

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#include <cstdlib>
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#include <verilated.h>
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#include "Vaccum.h"
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int main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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Vaccum *top = new Vaccum;
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while(!Verilated::gotFinish()) {
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top->eval();
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}
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top->final();
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delete top;
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return EXIT_SUCCESS;
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}
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‎cores/pipelined_order_book/verilog/Example.Project.topEntity/clash-manifest.json

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{
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"components": [
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"accum"
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],
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"dependencies": {
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"transitive": []
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},
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"domains": {
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"Dom50": {
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"active_edge": "Rising",
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"init_behavior": "Defined",
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"period": 20000,
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"reset_kind": "Asynchronous",
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"reset_polarity": "ActiveHigh"
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},
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"IntelSystem": {
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"active_edge": "Rising",
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"init_behavior": "Defined",
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"period": 10000,
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"reset_kind": "Asynchronous",
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"reset_polarity": "ActiveHigh"
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},
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"System": {
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"active_edge": "Rising",
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"init_behavior": "Defined",
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"period": 10000,
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"reset_kind": "Asynchronous",
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"reset_polarity": "ActiveHigh"
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},
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"XilinxSystem": {
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"active_edge": "Rising",
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"init_behavior": "Defined",
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"period": 10000,
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"reset_kind": "Synchronous",
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"reset_polarity": "ActiveHigh"
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}
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},
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"files": [
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{
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"name": "accum_shim.cpp",
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"sha256": "5abcaca52b57ad0e884cd74d67bf57e5193b1de914e0e8855b122d6c3af5ab12"
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},
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{
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"name": "accum_shim.cpp",
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"sha256": "5abcaca52b57ad0e884cd74d67bf57e5193b1de914e0e8855b122d6c3af5ab12"
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},
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{
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"name": "accum.sdc",
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"sha256": "872a13ebab22d7d64ce0ca6c4f93a5c1622f788d8269f1451bdba354b37c57a4"
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},
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{
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"name": "accum.v",
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"sha256": "289b55da1727d5d617102d84225f8ceba9cad6b7f42542883947b4eef64be0ff"
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}
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],
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"flags": [
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20,
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20
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],
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"hash": "b1e53b5786e353c37f9a585beee9d29b8906b6ecbda05e5c89c9ecc4e137fc10",
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"top_component": {
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"name": "accum",
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"ports_flat": [
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{
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"direction": "in",
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"domain": "Dom50",
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"is_clock": true,
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"name": "CLK",
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"type_name": "",
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"width": 1
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},
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{
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"direction": "in",
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"domain": "Dom50",
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"is_clock": false,
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"name": "RST",
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"type_name": "",
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"width": 1
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},
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{
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"direction": "in",
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"domain": "Dom50",
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"is_clock": false,
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"name": "EN",
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"type_name": "",
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"width": 1
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},
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{
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"direction": "in",
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"is_clock": false,
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"name": "DIN",
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"type_name": "[7:0]",
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"width": 8
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},
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{
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"direction": "out",
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"is_clock": false,
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"name": "DOUT",
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"type_name": "[7:0]",
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"width": 8
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}
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]
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},
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"version": "unstable"
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}

‎flake.lock

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