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| 1 | +From 91ac4786dac2d028662f3b0f49b3704c55c8eb19 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Marek Vasut <marek.vasut+renesas@mailbox.org> |
| 3 | +Date: Sat, 25 Apr 2026 22:17:57 +0200 |
| 4 | +Subject: [PATCH] PCI: rcar-gen4: Limit Max_Read_Request_Size and |
| 5 | + Max_Payload_Size to 256 Bytes |
| 6 | + |
| 7 | +R-Car Gen4 PCIe controller has a hardware limitation of 256 Bytes |
| 8 | +Max_Payload_Size (MPS). PCIe specification indicates that the MPS |
| 9 | +must not exceed minimum MPS of any element along the packet path. |
| 10 | +Force limit Max_Payload_Size to at most 256 Bytes for each device |
| 11 | +connected to this PCIe controller. |
| 12 | + |
| 13 | +R-Car Gen4 Reference Manual, chapter 104.4.8 Usage notes for |
| 14 | +MRRS (Max Read Request Size) states: |
| 15 | + Please set "Max Read Request Size" to 128 bytes or 256 bytes. |
| 16 | + If "Max Read Request Size" is set to anything other than the |
| 17 | + above, the transferred data will not match the expected value. |
| 18 | +This limitation also seems the apply to devices issuing MRd TLP. |
| 19 | +This limitation can be triggered by using non-HMB NVMe SSD with |
| 20 | +Max_Read_Request_Size 512 Bytes, for example Crucial P5 Plus. |
| 21 | +Any write into the SSD (MRd TLP issued by the SSD) longer than |
| 22 | +256 Bytes wraps around at 256 Byte boundary, and the same data |
| 23 | +are written into the SSD starting at offset 0 and at 256 Bytes. |
| 24 | +Force limit Max_Read_Request_Size to at most 256 Bytes for each |
| 25 | +device connected to this PCIe controller to avoid this behavior. |
| 26 | + |
| 27 | +An non-HMB (Host Memory Buffer) NVMe SSD can be identified using |
| 28 | +the following command. Affected SSD reports 'hmpre' field as 0: |
| 29 | +" |
| 30 | +$ nvme id-ctrl /dev/nvme0 | grep hmpre |
| 31 | +hmpre : 0 |
| 32 | +" |
| 33 | + |
| 34 | +The symptom is a read from the SSD which wraps around at 256 Byte |
| 35 | +boundary. The test for this symptom can be implemented by writing |
| 36 | +512 Byte of random data into the SSD and reading the data back. If |
| 37 | +the read back data repeat after 256 Bytes, the device is affected. |
| 38 | +" |
| 39 | +$ dd if=/dev/urandom of=/tmp/data.bin bs=256 count=2 \ |
| 40 | + dd if=/tmp/data.bin of=/dev/nvme0n1 bs=256 count=2 \ |
| 41 | + dd if=/dev/nvme0n1 bs=256 count=2 of=/tmp/readback.bin |
| 42 | +" |
| 43 | + |
| 44 | +Expected data: |
| 45 | +" |
| 46 | +$ hexdump -vC /tmp/data.bin |
| 47 | +00000000 97 81 b7 3b 0e 38 2b 4d a7 d3 e0 47 ff c2 4b ca |
| 48 | +00000010 c1 85 98 f0 4a ac 03 a0 3b ab f3 19 44 dd 06 8b |
| 49 | +... |
| 50 | +00000100 7a ce 3c b2 e1 d5 d9 11 88 63 10 59 76 3c dc 32 <-- random |
| 51 | +00000110 72 32 2a 7d a3 e1 aa 13 7c da 58 a1 7b 21 11 50 <-- data |
| 52 | +" |
| 53 | + |
| 54 | +Faulty readback, collected without this change in place: |
| 55 | +" |
| 56 | +$ hexdump -vC /tmp/readback.bin |
| 57 | +00000000 97 81 b7 3b 0e 38 2b 4d a7 d3 e0 47 ff c2 4b ca <---. |
| 58 | +00000010 c1 85 98 f0 4a ac 03 a0 3b ab f3 19 44 dd 06 8b <-. | |
| 59 | +... | | |
| 60 | +00000100 97 81 b7 3b 0e 38 2b 4d a7 d3 e0 47 ff c2 4b ca <-:-+- repeated |
| 61 | +00000110 c1 85 98 f0 4a ac 03 a0 3b ab f3 19 44 dd 06 8b <-+--- data |
| 62 | + ^^^ |
| 63 | + | |
| 64 | + '--- Repeat starts at offset 0x100 = 256 Bytes |
| 65 | +" |
| 66 | + |
| 67 | +Upstream-Status: Submitted [https://lore.kernel.org/linux-pci/20260519195219.189323-1-marek.vasut+renesas@mailbox.org/] |
| 68 | +Fixes: 0d0c551011df ("PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode") |
| 69 | +Cc: stable@vger.kernel.org |
| 70 | +Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> |
| 71 | +--- |
| 72 | +NOTE: - Possible EP mode limit of 128 Bytes is currently pending |
| 73 | + documentation team input |
| 74 | +V2: - Dispose of the reprogramming of MPS/MRRS altogether |
| 75 | + - Dispose of the entire fixup quirk |
| 76 | + - Replace both with bridge enable_device hook |
| 77 | + - Limit MPS/MRRS along the entire packet path to follow |
| 78 | + MRRS limitation requirement |
| 79 | +--- |
| 80 | + drivers/pci/controller/dwc/pcie-rcar-gen4.c | 51 +++++++++++++++++++++ |
| 81 | + 1 file changed, 51 insertions(+) |
| 82 | + |
| 83 | +diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c |
| 84 | +index 80778917d2ddd..13179d072f89a 100644 |
| 85 | +--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c |
| 86 | ++++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c |
| 87 | +@@ -305,6 +305,54 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) |
| 88 | + return rcar; |
| 89 | + } |
| 90 | + |
| 91 | ++static int rcar_gen4_pcie_enable_device(struct pci_host_bridge *bridge, |
| 92 | ++ struct pci_dev *dev) |
| 93 | ++{ |
| 94 | ++ /* |
| 95 | ++ * R-Car Gen4 PCIe controller has a hardware limitation of 256 Bytes |
| 96 | ++ * Max_Payload_Size (MPS). PCIe specification indicates that the MPS |
| 97 | ++ * must not exceed minimum MPS of any element along the packet path. |
| 98 | ++ * Force limit Max_Payload_Size to at most 256 Bytes for each device |
| 99 | ++ * connected to this PCIe controller. |
| 100 | ++ * |
| 101 | ++ * For details, refer to chapter "104.1.1 Features" in either of: |
| 102 | ++ * R-Car S4 R19UH0161EJ0130 Rev.1.30 Jun. 16, 2025 or |
| 103 | ++ * R-Car V4H R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 or |
| 104 | ++ * R-Car V4M R19UH0217EJ0100 Rev.1.00 Dec. 12, 2025. |
| 105 | ++ */ |
| 106 | ++ if (pcie_get_mps(dev) > 256) { |
| 107 | ++ pci_info(dev, "Limiting MPS to 256 bytes\n"); |
| 108 | ++ pcie_set_mps(dev, 256); |
| 109 | ++ } |
| 110 | ++ |
| 111 | ++ /* |
| 112 | ++ * R-Car Gen4 Reference Manual, chapter 104.4.8 Usage notes for |
| 113 | ++ * MRRS (Max Read Request Size) states: |
| 114 | ++ * Please set "Max Read Request Size" to 128 bytes or 256 bytes. |
| 115 | ++ * If "Max Read Request Size" is set to anything other than the |
| 116 | ++ * above, the transferred data will not match the expected value. |
| 117 | ++ * This limitation also seems the apply to devices issuing MRd TLP. |
| 118 | ++ * This limitation can be triggered by using non-HMB NVMe SSD with |
| 119 | ++ * Max_Read_Request_Size 512 Bytes, for example Crucial P5 Plus. |
| 120 | ++ * Any write into the SSD (MRd TLP issued by the SSD) longer than |
| 121 | ++ * 256 Bytes wraps around at 256 Byte boundary, and the same data |
| 122 | ++ * are written into the SSD starting at offset 0 and at 256 Bytes. |
| 123 | ++ * Force limit Max_Read_Request_Size to at most 256 Bytes for each |
| 124 | ++ * device connected to this PCIe controller to avoid this behavior. |
| 125 | ++ * |
| 126 | ++ * For details, refer to aforementioned chapter in either of: |
| 127 | ++ * R-Car S4 R19UH0161EJ0130 Rev.1.30 Jun. 16, 2025 or |
| 128 | ++ * R-Car V4H R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 or |
| 129 | ++ * R-Car V4M R19UH0217EJ0100 Rev.1.00 Dec. 12, 2025, |
| 130 | ++ */ |
| 131 | ++ if (pcie_get_readrq(dev) > 256) { |
| 132 | ++ pci_info(dev, "Limiting MRRS to 256 bytes\n"); |
| 133 | ++ pcie_set_readrq(dev, 256); |
| 134 | ++ } |
| 135 | ++ |
| 136 | ++ return 0; |
| 137 | ++} |
| 138 | ++ |
| 139 | + /* Host mode */ |
| 140 | + static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) |
| 141 | + { |
| 142 | +@@ -313,6 +361,9 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) |
| 143 | + int ret; |
| 144 | + u32 val; |
| 145 | + |
| 146 | ++ if (pp->bridge) |
| 147 | ++ pp->bridge->enable_device = rcar_gen4_pcie_enable_device; |
| 148 | ++ |
| 149 | + gpiod_set_value_cansleep(dw->pe_rst, 1); |
| 150 | + |
| 151 | + ret = rcar_gen4_pcie_common_init(rcar); |
| 152 | +-- |
| 153 | +2.53.0 |
| 154 | + |
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