[DAG] computeKnownFPClass - Add handling for AssertNoFPClass (llvm#190185)

Resolves llvm#189478

Adds code to handle AssertNoFPClass in computeKnownFPClass and adds IR
test coverage for RISC-V.

Author: joaovam

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -6121,6 +6121,14 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
     Known.fabs();
     break;
   }
+  case ISD::AssertNoFPClass: {
+    Known = computeKnownFPClass(Op.getOperand(0), DemandedElts,
+                                InterestedClasses, Depth + 1);
+    FPClassTest AssertedClasses =
+        static_cast<FPClassTest>(Op->getConstantOperandVal(1));
+    Known.KnownFPClasses &= ~AssertedClasses;
+    break;
+  }
   default:
     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
         Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {

llvm/test/CodeGen/RISCV/known-fpclass.ll

@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d < %s | FileCheck %s
+
+define <vscale x 4 x i1> @test_full_pinf_vs_pinf(<vscale x 4 x float> nofpclass(pinf) %a) {
+; CHECK-LABEL: test_full_pinf_vs_pinf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 512)
+  ret <vscale x 4 x i1> %class
+}
+
+define <vscale x 4 x i1> @test_full_fabs_nan_vs_nan(<vscale x 4 x float> nofpclass(nan) %a) {
+; CHECK-LABEL: test_full_fabs_nan_vs_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %abs = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %a)
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %abs, i32 3)
+  ret <vscale x 4 x i1> %class
+}
+
+define <vscale x 4 x i1> @test_partial_nan_from_nan_pinf(<vscale x 4 x float> nofpclass(nan) %a) {
+; CHECK-LABEL: test_partial_nan_from_nan_pinf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 128
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
+; CHECK-NEXT:    ret
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 515)
+  ret <vscale x 4 x i1> %class
+}
+
+define <vscale x 4 x i1> @test_partial_pinf_from_inf(<vscale x 4 x float> nofpclass(pinf) %a) {
+; CHECK-LABEL: test_partial_pinf_from_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 64
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
+; CHECK-NEXT:    ret
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 768)
+  ret <vscale x 4 x i1> %class
+}
+
+define <vscale x 4 x i1> @test_no_overlap_pinf_vs_nan(<vscale x 4 x float> nofpclass(pinf) %a) {
+; CHECK-LABEL: test_no_overlap_pinf_vs_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 3)
+  ret <vscale x 4 x i1> %class
+}
+
+define <vscale x 4 x i1> @test_no_overlap_nan_vs_pinf(<vscale x 4 x float> nofpclass(nan) %a) {
+; CHECK-LABEL: test_no_overlap_nan_vs_pinf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 128
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
+; CHECK-NEXT:    ret
+  %class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 512)
+  ret <vscale x 4 x i1> %class
+}