realsenseai
diff --git a/‎kernel/nvidia/5.0.2/0015-Adding-max96712-support-for-D4xx.patch‎
Lines changed: 2 additions & 2 deletions b/‎kernel/nvidia/5.0.2/0015-Adding-max96712-support-for-D4xx.patch‎
Lines changed: 2 additions & 2 deletions
@@ -271,13 +271,13 @@ index 8081385f0..3de1643bc 100644
 +		{MAX96712_MIPI_TX10_ADDR, 0x40}, //0x94a - MIPI lane count
 +		{MAX96712_MIPI_PHY3_ADDR, 0xe4}, //0x8A3, Lower phys to lower lanes
 +
-+		/* Put DPLL for ctrl 1 and 2 in reset (config_soft_rst_n = 0) before changing MIPI lane rates */
++		/* Put DPLL in reset before changing MIPI lane rates */
 +		{MAX96712_DPLL_0_ADDR, 0xF4}, //0x1D00
 +
 +		/* 1500Mbps/lane on port A */
 +		{MAX96712_BACKTOP25_ADDR, 0x2f}, //0x418
 +
-+		/* Release DPLL reset (config_soft_rst_n = 1) */
++		/* Release DPLL reset */
 +		{MAX96712_DPLL_0_ADDR, 0xF5}, //0x1D00
 +
 +		/* ALT2_MEM_MAP8 */
Original file line number	Diff line number	Diff line change
`@@ -271,13 +271,13 @@ index 8081385f0..3de1643bc 100644`
`271`	`271`	`+ {MAX96712_MIPI_TX10_ADDR, 0x40}, //0x94a - MIPI lane count`
`272`	`272`	`+ {MAX96712_MIPI_PHY3_ADDR, 0xe4}, //0x8A3, Lower phys to lower lanes`
`273`	`273`	`+`
`274`		`-+ /* Put DPLL for ctrl 1 and 2 in reset (config_soft_rst_n = 0) before changing MIPI lane rates */`
	`274`	`++ /* Put DPLL in reset before changing MIPI lane rates */`
`275`	`275`	`+ {MAX96712_DPLL_0_ADDR, 0xF4}, //0x1D00`
`276`	`276`	`+`
`277`	`277`	`+ /* 1500Mbps/lane on port A */`
`278`	`278`	`+ {MAX96712_BACKTOP25_ADDR, 0x2f}, //0x418`
`279`	`279`	`+`
`280`		`-+ /* Release DPLL reset (config_soft_rst_n = 1) */`
	`280`	`++ /* Release DPLL reset */`
`281`	`281`	`+ {MAX96712_DPLL_0_ADDR, 0xF5}, //0x1D00`
`282`	`282`	`+`
`283`	`283`	`+ /* ALT2_MEM_MAP8 */`