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src/1_58bit_mul.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ module systolic_array (
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output wire [7:0] out
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);
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localparam SLICES = 2;
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localparam SLICES = 1;
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localparam SLICE_BITS = $clog2(SLICES);
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localparam SLICES_MINUS_1 = SLICES - 1;
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localparam W = 1 * SLICES;
@@ -153,6 +153,6 @@ module systolic_array (
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end
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endgenerate
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// assign out = out_queue[out_queue_counter] >> 8;
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assign out = out_queue[out_queue_counter][7:0];
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assign out = out_queue[out_queue_counter] >> 8;
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// assign out = out_queue[out_queue_counter][7:0];
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endmodule

test/test.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@
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from cocotb.triggers import ClockCycles
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from utils import *
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COMPUTE_SLICES = 2
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COMPUTE_SLICES = 1
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COMPUTE_BLOCK_WIDTH = 1*COMPUTE_SLICES
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COMPUTE_BLOCK_HEIGHT = 4*COMPUTE_SLICES
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def OUT(v):
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# return v >> 8
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return s8_to_i32(v & 255)
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return v >> 8
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# return s8_to_i32(v & 255)
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@cocotb.test()
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async def test_1(dut):

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