I implemented TLS processing using the MbedTLS Stack from FSP v6.4.0.
I enabled the MBEDTLS_SHA256_ALT feature to use the hardening hash feature.
renesas.github.io/.../group___r_m___p_s_a___c_r_y_p_t_o.html
However, in this case, if multiple mbedtls_sha256_update calls are made during the hashing process, and the following conditions are met in mbedtls_sha256_finish, an infinite register change wait will occur.
ra\fsp\src\rm_psa_crypto\sha256_alt.c
line: 884~892
else
{ /* If there is no data in the unaligned ctx buffer and no data in the aligned buffer
then this is case of 0 total length passed in. */
ctx->sce_operation_state = SCE_OEM_CMD_HASH_ONESHOT;
if( ( ret = mbedtls_internal_sha256_process_ext(ctx, ctx->rsip_buffer, 0 ) ) != 0)
{
goto exit;
}
}
This condition is reached when multiple mbedtls_sha256_update calls have been made and mbedtls_sha256_finish is called when the total size of the input data reaches 0x80 (128).
"ctx->total[0] == 0x80"
The infinite register change wait occurs in the following section of HW_SCE_ShaGenerateMessageDigestFinalSub.
WAIT_STS(REG_2030H, 4, 1);
This issue occurs when the third argument of mbedtls_internal_sha256_process_ext is set to 0.
It seems the input data is incorrect, causing an infinite loop due to a register change wait.
The following MCUs have been found to have this issue:
RA8T2: RSIP-E50D (using FreeRTOS)
Disabling MBEDTLS_SHA256_ALT and performing hash processing through software allows for successful hash processing, but the hash processing speed is slow, and I would like to improve this issue.
I have already posted this issue to Renesas Engineering Community.
The person in charge confirmed this issue and concluded it was a bug.
Therefore, I was asked to post it here.
https://community.renesas.com/mcu/ra/f/forum/59019/when-mbedtls_sha256_alt-is-enabled-sha-256-final-digest-process-waits-for-register-changes
Please fix this issue.
I implemented TLS processing using the MbedTLS Stack from FSP v6.4.0.
I enabled the MBEDTLS_SHA256_ALT feature to use the hardening hash feature.
renesas.github.io/.../group___r_m___p_s_a___c_r_y_p_t_o.html
However, in this case, if multiple mbedtls_sha256_update calls are made during the hashing process, and the following conditions are met in mbedtls_sha256_finish, an infinite register change wait will occur.
ra\fsp\src\rm_psa_crypto\sha256_alt.c
line: 884~892
This condition is reached when multiple mbedtls_sha256_update calls have been made and mbedtls_sha256_finish is called when the total size of the input data reaches 0x80 (128).
"ctx->total[0] == 0x80"
The infinite register change wait occurs in the following section of HW_SCE_ShaGenerateMessageDigestFinalSub.
This issue occurs when the third argument of mbedtls_internal_sha256_process_ext is set to 0.
It seems the input data is incorrect, causing an infinite loop due to a register change wait.
The following MCUs have been found to have this issue:
RA8T2: RSIP-E50D (using FreeRTOS)
Disabling MBEDTLS_SHA256_ALT and performing hash processing through software allows for successful hash processing, but the hash processing speed is slow, and I would like to improve this issue.
I have already posted this issue to Renesas Engineering Community.
The person in charge confirmed this issue and concluded it was a bug.
Therefore, I was asked to post it here.
https://community.renesas.com/mcu/ra/f/forum/59019/when-mbedtls_sha256_alt-is-enabled-sha-256-final-digest-process-waits-for-register-changes
Please fix this issue.