RA4M1: PLL divider /4 generates prohibited PLLCCR2.PLODIV encoding

[aracosta1]

I found what appears to be an incorrect PLL divider encoding for RA4M1 when using FSP.

The issue was reproduced with:

MCU: Renesas RA4M1
FSP versions: 6.2.0 and 6.5.1
Main oscillator: 16 MHz
PLL multiplier: ×8
PLL divider: /4

Expected PLL output: 16 MHz × 8 / 4 = 32 MHz

Observed behavior

FSP generates:
#define BSP_CFG_PLL_DIV BSP_CLOCKS_PLL_DIV_4

and BSP_CLOCKS_PLL_DIV_4 is defined as:
#define BSP_CLOCKS_PLL_DIV_4 (3)

For RA4M1, BSP_FEATURE_CGC_PLLCCR_TYPE is 2, so FSP writes the divider value directly into PLLCCR2.PLODIV[1:0]:
#define BSP_PRV_PLLCCR ((BSP_PRV_PLLCCR2_PLLMUL & 0x1F) | (BSP_CFG_PLL_DIV << 6))

This results in:
PLLCCR2.PLODIV[1:0] = 11b
According to the RA4M1 hardware manual, PLLCCR2.PLODIV[1:0] is encoded as:

> 00b = Reserved
> 01b = /2
> 10b = /4
> 11b = Prohibited / reserved

Therefore, for PLL output divider /4, FSP should write:
PLODIV[1:0] = 10b

not:
PLODIV[1:0] = 11b

Expected behavior

For RA4M1, selecting PLL divider /4 should generate a valid PLLCCR2.PLODIV value:
PLODIV = 2

Alternatively, if the generic BSP_CLOCKS_PLL_DIV_4 = 3 value is intended for another MCU family or register layout, FSP should remap it correctly when BSP_FEATURE_CGC_PLLCCR_TYPE == 2.

Steps to reproduce

Create an RA4M1 project.
Use FSP 6.2.0 or FSP 6.5.1.
Configure Main Oscillator as 16 MHz.
Configure PLL multiplier as ×8.
Configure PLL divider as /4.
Generate the project.
Inspect the generated clock configuration / PLLCCR2 value.
Observe that BSP_CFG_PLL_DIV resolves to 3, causing PLLCCR2.PLODIV[1:0] = 11b.

[renesas-austin-hansen]

This is also applicable to RA4W1 as it is the only other device with BSP_FEATURE_CGC_PLLCCR_TYPE (2).

Tracked internally via FSPRA-6027