Skip to content

Commit 979b160

Browse files
rgallaispouSTMrgallaispouSTM
committed
dts: arm: st: f4: add DFSDM peripheral support
Add the DFSDM peripheral to STM32F4xx series. Depending on the hardware, there is one or two instances of DFSDM, with a total of 2 or 6 filters respectively: $ rg -c DFSDM._FLT._IRQn\\s stm32cube/stm32f4xx/soc/ | sort stm32cube/stm32f4xx/soc/stm32f412cx.h:2 stm32cube/stm32f4xx/soc/stm32f412rx.h:2 stm32cube/stm32f4xx/soc/stm32f412vx.h:2 stm32cube/stm32f4xx/soc/stm32f412zx.h:2 stm32cube/stm32f4xx/soc/stm32f413xx.h:6 stm32cube/stm32f4xx/soc/stm32f423xx.h:6 Audio clock 'aclk' has not been instanciated since it depends on board configuration. Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
1 parent e17d4c6 commit 979b160

2 files changed

Lines changed: 82 additions & 0 deletions

File tree

‎dts/arm/st/f4/stm32f412.dtsi‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,37 @@
253253
master-can-reg = <0x40006400>;
254254
status = "disabled";
255255
};
256+
257+
dfsdm1: dfsdm@40016000 {
258+
compatible = "st,stm32-dfsdm";
259+
reg = <0x40016000 0x400>;
260+
clocks = <&rcc STM32_CLOCK(APB2, 24)>;
261+
clock-names = "pclk";
262+
resets = <&rctl STM32_RESET(APB2, 24)>;
263+
#address-cells = <1>;
264+
#size-cells = <0>;
265+
status = "disabled";
266+
267+
pdm0: filter@0 {
268+
compatible = "st,stm32-dfsdm-dmic";
269+
reg = <0>;
270+
interrupts = <61 0>;
271+
filter-order = <5>;
272+
#address-cells = <1>;
273+
#size-cells = <0>;
274+
status = "disabled";
275+
};
276+
277+
pdm1: filter@1 {
278+
compatible = "st,stm32-dfsdm-dmic";
279+
reg = <1>;
280+
interrupts = <62 0>;
281+
filter-order = <5>;
282+
#address-cells = <1>;
283+
#size-cells = <0>;
284+
status = "disabled";
285+
};
286+
};
256287
};
257288

258289
die_temp: dietemp {

‎dts/arm/st/f4/stm32f413.dtsi‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,5 +108,56 @@
108108
status = "disabled";
109109
};
110110
};
111+
112+
dfsdm2: dfsdm@40016400 {
113+
compatible = "st,stm32-dfsdm";
114+
reg = <0x40016400 0x400>;
115+
clocks = <&rcc STM32_CLOCK(APB2, 25)>;
116+
clock-names = "pclk";
117+
resets = <&rctl STM32_RESET(APB2, 25)>;
118+
#address-cells = <1>;
119+
#size-cells = <0>;
120+
status = "disabled";
121+
122+
pdm2: filter@0 {
123+
compatible = "st,stm32-dfsdm-dmic";
124+
reg = <0>;
125+
interrupts = <98 0>;
126+
filter-order = <5>;
127+
#address-cells = <1>;
128+
#size-cells = <0>;
129+
status = "disabled";
130+
};
131+
132+
pdm3: filter@1 {
133+
compatible = "st,stm32-dfsdm-dmic";
134+
reg = <1>;
135+
interrupts = <99 0>;
136+
filter-order = <5>;
137+
#address-cells = <1>;
138+
#size-cells = <0>;
139+
status = "disabled";
140+
};
141+
142+
pdm4: filter@2 {
143+
compatible = "st,stm32-dfsdm-dmic";
144+
reg = <2>;
145+
interrupts = <100 0>;
146+
filter-order = <5>;
147+
#address-cells = <1>;
148+
#size-cells = <0>;
149+
status = "disabled";
150+
};
151+
152+
pdm5: filter@3 {
153+
compatible = "st,stm32-dfsdm-dmic";
154+
reg = <3>;
155+
interrupts = <101 0>;
156+
filter-order = <5>;
157+
#address-cells = <1>;
158+
#size-cells = <0>;
159+
status = "disabled";
160+
};
161+
};
111162
};
112163
};

0 commit comments

Comments
 (0)