Skip to content

Commit 06a08a5

Browse files
vlsunilatishp04
vlsunil
authored and
atishp04
committed
Introduce CPPC extension
ACPI defines the Collaborative Processor Performance Control (CPPC), a mechanism which is an abstract and flexible mechanism for the Operating System to collaborate with an entity in the platform to manage the performance of the processors. The SBI CPPC extension provides an abstraction to access CPPC registers through SBI calls. Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Atish Patra <[email protected]> Signed-off-by: Sunil V L <[email protected]>
1 parent 503c147 commit 06a08a5

File tree

1 file changed

+171
-0
lines changed

1 file changed

+171
-0
lines changed

‎riscv-sbi.adoc

Lines changed: 171 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ https://creativecommons.org/licenses/by/4.0/.
6767
* Added sbi_pmu_counter_fw_read_hi() in SBI PMU extension
6868
* Reserved space for SBI implementation specific firmware events
6969
* Added SBI system suspend extension
70+
* Added SBI CPPC extension
7071

7172
=== Version 1.0.0
7273

@@ -151,7 +152,10 @@ This specification uses the following terms and abbreviations:
151152
|===
152153
| Term | Meaning
153154

155+
| ACPI | Advanced Configuration and Power Interface
154156
| ASID | Address Space Identifier
157+
| BMC | Baseboard Management Controller
158+
| CPPC | Collaborative Processor Performance Control
155159
| EID | Extension ID
156160
| FID | Function ID
157161
| HSM | Hart State Management
@@ -2012,6 +2016,173 @@ The possible error codes returned in `sbiret.error` are shown in
20122016
| sbi_system_suspend | 2.0 | 0 | 0x53555350
20132017
|===
20142018

2019+
== CPPC Extension (EID #0x43505043 "CPPC")
2020+
2021+
ACPI defines the Collaborative Processor Performance Control (CPPC) mechanism,
2022+
which is an abstract and flexible mechanism for the supervisor-mode
2023+
power-management software to collaborate with an entity in the platform to
2024+
manage the performance of the processors.
2025+
2026+
The SBI CPPC extension provides an abstraction to access the CPPC registers
2027+
through SBI calls. The CPPC registers can be memory locations shared with a
2028+
separate platform entity such as a BMC. Even though CPPC is defined in the ACPI
2029+
specification, it may be possible to implement a CPPC driver based on
2030+
Device Tree.
2031+
2032+
<<table_cppc_registers>> defines 32-bit identifiers for all CPPC registers
2033+
to be used by the SBI CPPC functions. The first half of the 32-bit register
2034+
space corresponds to the registers as defined by the ACPI specification.
2035+
The second half provides the information not defined in the ACPI specification,
2036+
but is additionally required by the supervisor-mode power-management software.
2037+
2038+
[#table_cppc_registers]
2039+
.CPPC Registers
2040+
[cols="1,2,1,1,3", width=100%, align="center", options="header"]
2041+
|===
2042+
| Register ID | Register | Bit Width | Attribute | Description
2043+
| 0x00000000 | HighestPerformance | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.1
2044+
| 0x00000001 | NominalPerformance | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.2
2045+
| 0x00000002 | LowestNonlinearPerformance | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.4
2046+
| 0x00000003 | LowestPerformance | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.5
2047+
| 0x00000004 | GuaranteedPerformanceRegister | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.6
2048+
| 0x00000005 | DesiredPerformanceRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.2.3
2049+
| 0x00000006 | MinimumPerformanceRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.2.2
2050+
| 0x00000007 | MaximumPerformanceRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.2.1
2051+
| 0x00000008 | PerformanceReductionToleranceRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.2.4
2052+
| 0x00000009 | TimeWindowRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.2.5
2053+
| 0x0000000A | CounterWraparoundTime | 32 / 64 | Read-only | ACPI Spec 6.5: 8.4.6.1.3.1
2054+
| 0x0000000B | ReferencePerformanceCounterRegister | 32 / 64 | Read-only | ACPI Spec 6.5: 8.4.6.1.3.1
2055+
| 0x0000000C | DeliveredPerformanceCounterRegister | 32 / 64 | Read-only | ACPI Spec 6.5: 8.4.6.1.3.1
2056+
| 0x0000000D | PerformanceLimitedRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.3.2
2057+
| 0x0000000E | CPPCEnableRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.4
2058+
| 0x0000000F | AutonomousSelectionEnable | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.5
2059+
| 0x00000010 | AutonomousActivityWindowRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.6
2060+
| 0x00000011 | EnergyPerformancePreferenceRegister | 32 | Read / Write | ACPI Spec 6.5: 8.4.6.1.7
2061+
| 0x00000012 | ReferencePerformance | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.3
2062+
| 0x00000013 | LowestFrequency | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.7
2063+
| 0x00000014 | NominalFrequency | 32 | Read-only | ACPI Spec 6.5: 8.4.6.1.1.7
2064+
| 0x00000015 - 0x7FFFFFFF | | | | Reserved for future use.
2065+
| 0x80000000 | TransitionLatency | 32 | Read-only | Provides the maximum (worst-case) performance
2066+
state transition latency in nanoseconds.
2067+
| 0x80000001 - 0xFFFFFFFF | | | | Reserved for future use.
2068+
|===
2069+
2070+
=== Function: Probe CPPC register (FID #0)
2071+
2072+
[source, C]
2073+
----
2074+
struct sbiret sbi_cppc_probe(uint32_t cppc_reg_id)
2075+
----
2076+
Probe whether the CPPC register as specified by the `cppc_reg_id` parameter
2077+
is implemented or not by the platform.
2078+
2079+
If the register is implemented, `sbiret.value` will contain the register
2080+
width. If the register is not implemented, `sbiret.value` will be set to 0.
2081+
2082+
The possible error codes returned in `sbiret.error` are shown in
2083+
<<table_cppc_probe_errors>>.
2084+
2085+
[#table_cppc_probe_errors]
2086+
.CPPC Probe Errors
2087+
[cols="1,2", width=100%, align="center", options="header"]
2088+
|===
2089+
| Error code | Description
2090+
| SBI_SUCCESS | Probe completed successfully.
2091+
| SBI_ERR_INVALID_PARAM | `cppc_reg_id` is reserved.
2092+
| SBI_ERR_FAILED | The probe request failed for unspecified or
2093+
unknown other reasons.
2094+
|===
2095+
2096+
=== Function: Read CPPC register (FID #1)
2097+
2098+
[source, C]
2099+
----
2100+
struct sbiret sbi_cppc_read(uint32_t cppc_reg_id)
2101+
----
2102+
Reads the register as specified in the `cppc_reg_id` parameter and returns the
2103+
value in `sbiret.value`. When supervisor mode XLEN is 32, the `sbiret.value`
2104+
will only contain the lower 32 bits of the CPPC register value.
2105+
2106+
The possible error codes returned in `sbiret.error` are shown in
2107+
<<table_cppc_read_errors>>.
2108+
2109+
[#table_cppc_read_errors]
2110+
.CPPC Read Errors
2111+
[cols="1,2", width=100%, align="center", options="header"]
2112+
|===
2113+
| Error code | Description
2114+
| SBI_SUCCESS | Read completed successfully.
2115+
| SBI_ERR_INVALID_PARAM | `cppc_reg_id` is reserved.
2116+
| SBI_ERR_NOT_SUPPORTED | `cppc_reg_id` is not implemented by the platform.
2117+
| SBI_ERR_DENIED | `cppc_reg_id` is a write-only register.
2118+
| SBI_ERR_FAILED | The read request failed for unspecified or
2119+
unknown other reasons.
2120+
|===
2121+
2122+
=== Function: Read CPPC register high bits (FID #2)
2123+
2124+
[source, C]
2125+
----
2126+
struct sbiret sbi_cppc_read_hi(uint32_t cppc_reg_id)
2127+
----
2128+
Reads the upper 32-bit value of the register specified in the `cppc_reg_id`
2129+
parameter and returns the value in `sbiret.value`. This function always
2130+
returns zero in `sbiret.value` when supervisor mode XLEN is 64 or higher.
2131+
2132+
The possible error codes returned in `sbiret.error` are shown in
2133+
<<table_cppc_read_hi_errors>>.
2134+
2135+
[#table_cppc_read_hi_errors]
2136+
.CPPC Read Hi Errors
2137+
[cols="1,2", width=100%, align="center", options="header"]
2138+
|===
2139+
| Error code | Description
2140+
| SBI_SUCCESS | Read completed successfully.
2141+
| SBI_ERR_INVALID_PARAM | `cppc_reg_id` is reserved.
2142+
| SBI_ERR_NOT_SUPPORTED | `cppc_reg_id` is not implemented by the platform.
2143+
| SBI_ERR_DENIED | `cppc_reg_id` is a write-only register.
2144+
| SBI_ERR_FAILED | The read request failed for unspecified or
2145+
unknown other reasons.
2146+
|===
2147+
2148+
=== Function: Write to CPPC register (FID #3)
2149+
2150+
[source, C]
2151+
----
2152+
struct sbiret sbi_cppc_write(uint32_t cppc_reg_id, uint64_t val)
2153+
----
2154+
Writes the value passed in the `val` parameter to the register as
2155+
specified in the `cppc_reg_id` parameter.
2156+
2157+
The possible error codes returned in `sbiret.error` are shown in
2158+
<<table_cppc_write_errors>>.
2159+
2160+
[#table_cppc_write_errors]
2161+
.CPPC Write Errors
2162+
[cols="1,2", width=100%, align="center", options="header"]
2163+
|===
2164+
| Error code | Description
2165+
| SBI_SUCCESS | Write completed successfully.
2166+
| SBI_ERR_INVALID_PARAM | `cppc_reg_id` is reserved.
2167+
| SBI_ERR_NOT_SUPPORTED | `cppc_reg_id` is not implemented by the platform.
2168+
| SBI_ERR_DENIED | `cppc_reg_id` is a read-only register.
2169+
| SBI_ERR_FAILED | The write request failed for unspecified or
2170+
unknown other reasons.
2171+
|===
2172+
2173+
=== Function Listing
2174+
2175+
[#table_cppc_function_list]
2176+
.CPPC Function List
2177+
[cols="3,2,1,2", width=80%, align="center", options="header"]
2178+
|===
2179+
| Function Name | SBI Version | FID | EID
2180+
| sbi_cppc_probe | 2.0 | 0 | 0x43505043
2181+
| sbi_cppc_read | 2.0 | 1 | 0x43505043
2182+
| sbi_cppc_read_hi | 2.0 | 2 | 0x43505043
2183+
| sbi_cppc_write | 2.0 | 3 | 0x43505043
2184+
|===
2185+
20152186
== Experimental SBI Extension Space (EIDs #0x08000000 - #0x08FFFFFF)
20162187

20172188
No management.

0 commit comments

Comments
 (0)