Description of trPibEnable does not mention a flush.

[Lauterbach-MIS]

In contrast to other tr*Enable fields in the RISC-V Trace Control Interface Specification, trPibEnable does not describe how to flush the component.

Though the 'Enabling and Disabling' chapter is referenced, some people might jump to the wrong conclusion and could assume that the transition of trPibEnable from 1 to 0 cuts off the transmission of trace data immediately.

To make this easier to understand, I would propose to adopt the field description of trRamEnable.

[mipsrobert]

Thanks @Lauterbach-MIS - I will keep issue open and change text together with other smaller/clarifying changes. RVI does not have good process of providing different versions/revisions/updates of ratified specs - doing it too often would create problems.