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aswatermanaswaterman
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Clean up VA size handling
Representing the VA size as a feature set rather than an integer allows for internal inconsistency and is inelegant.
1 parent fd604be commit 1bf8358

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8 files changed

+38
-52
lines changed

8 files changed

+38
-52
lines changed

‎riscv/csrs.cc‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -431,7 +431,7 @@ reg_t cause_csr_t::read() const noexcept {
431431
// implement class base_status_csr_t
432432
base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr):
433433
csr_t(proc, addr),
434-
has_page(proc->extension_enabled_const('S') && proc->supports_impl(IMPL_MMU)),
434+
has_page(proc->extension_enabled_const('S') && proc->has_mmu()),
435435
sstatus_write_mask(compute_sstatus_write_mask()),
436436
sstatus_read_mask(sstatus_write_mask | SSTATUS_UBE | SSTATUS_UXL
437437
| (proc->get_const_xlen() == 32 ? SSTATUS32_SD : SSTATUS64_SD)) {
@@ -1005,7 +1005,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
10051005
| (1 << CAUSE_STORE_ACCESS)
10061006
| (1 << CAUSE_USER_ECALL)
10071007
| (1 << CAUSE_SUPERVISOR_ECALL)
1008-
| (proc->supports_impl(IMPL_MMU) ? mmu_exceptions : 0)
1008+
| (proc->has_mmu() ? mmu_exceptions : 0)
10091009
| (proc->extension_enabled('H') ? hypervisor_exceptions : 0)
10101010
| (1 << CAUSE_SOFTWARE_CHECK_FAULT)
10111011
| (1 << CAUSE_HARDWARE_ERROR_FAULT)
@@ -1088,7 +1088,7 @@ base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr):
10881088
}
10891089

10901090
bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept {
1091-
const reg_t newval = proc->supports_impl(IMPL_MMU) ? compute_new_satp(val) : 0;
1091+
const reg_t newval = proc->has_mmu() ? compute_new_satp(val) : 0;
10921092
if (newval != read())
10931093
proc->get_mmu()->flush_tlb();
10941094
return basic_csr_t::unlogged_write(newval);
@@ -1097,16 +1097,16 @@ bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept {
10971097
bool base_atp_csr_t::satp_valid(reg_t val) const noexcept {
10981098
if (proc->get_xlen() == 32) {
10991099
switch (get_field(val, SATP32_MODE)) {
1100-
case SATP_MODE_SV32: return proc->supports_impl(IMPL_MMU_SV32);
11011100
case SATP_MODE_OFF: return true;
1101+
case SATP_MODE_SV32: return proc->get_max_vaddr_bits() >= 32;
11021102
default: return false;
11031103
}
11041104
} else {
11051105
switch (get_field(val, SATP64_MODE)) {
1106-
case SATP_MODE_SV39: return proc->supports_impl(IMPL_MMU_SV39);
1107-
case SATP_MODE_SV48: return proc->supports_impl(IMPL_MMU_SV48);
1108-
case SATP_MODE_SV57: return proc->supports_impl(IMPL_MMU_SV57);
11091106
case SATP_MODE_OFF: return true;
1107+
case SATP_MODE_SV39: return proc->get_max_vaddr_bits() >= 39;
1108+
case SATP_MODE_SV48: return proc->get_max_vaddr_bits() >= 48;
1109+
case SATP_MODE_SV57: return proc->get_max_vaddr_bits() >= 57;
11101110
default: return false;
11111111
}
11121112
}
@@ -1345,9 +1345,9 @@ bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept {
13451345
(proc->supports_impl(IMPL_MMU_VMID) ? HGATP64_VMID : 0);
13461346

13471347
if (get_field(val, HGATP64_MODE) == HGATP_MODE_OFF ||
1348-
(proc->supports_impl(IMPL_MMU_SV39) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV39X4) ||
1349-
(proc->supports_impl(IMPL_MMU_SV48) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV48X4) ||
1350-
(proc->supports_impl(IMPL_MMU_SV57) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV57X4))
1348+
(proc->get_max_vaddr_bits() >= 39 && get_field(val, HGATP64_MODE) == HGATP_MODE_SV39X4) ||
1349+
(proc->get_max_vaddr_bits() >= 48 && get_field(val, HGATP64_MODE) == HGATP_MODE_SV48X4) ||
1350+
(proc->get_max_vaddr_bits() >= 57 && get_field(val, HGATP64_MODE) == HGATP_MODE_SV57X4))
13511351
mask |= HGATP64_MODE;
13521352
}
13531353
mask &= ~(reg_t)3;
@@ -2037,7 +2037,7 @@ hstatus_csr_t::hstatus_csr_t(processor_t* const proc, const reg_t addr):
20372037
bool hstatus_csr_t::unlogged_write(const reg_t val) noexcept {
20382038
const reg_t mask = (proc->extension_enabled(EXT_SVUKTE) ? HSTATUS_HUKTE : 0)
20392039
| HSTATUS_VTSR | HSTATUS_VTW
2040-
| (proc->supports_impl(IMPL_MMU) ? HSTATUS_VTVM : 0)
2040+
| (proc->has_mmu() ? HSTATUS_VTVM : 0)
20412041
| (proc->extension_enabled(EXT_SSNPM) ? HSTATUS_HUPMM : 0)
20422042
| HSTATUS_HU | HSTATUS_SPVP | HSTATUS_SPV | HSTATUS_GVA;
20432043

‎riscv/decode_macros.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
163163
#define require_rv32 require(xlen == 32)
164164
#define require_extension(s) require(p->extension_enabled(s))
165165
#define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B));
166-
#define require_impl(s) require(p->supports_impl(s))
167166
#define require_fp STATE.fflags->verify_permissions(insn, false)
168167
#define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS))
169168
#define require_vector_vs require(p->any_vector_extensions() && STATE.sstatus->enabled(SSTATUS_VS))

‎riscv/insns/sfence_inval_ir.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('S');
22
require_extension(EXT_SVINVAL);
3-
require_impl(IMPL_MMU);
3+
require(p->has_mmu());
44
require_privilege_hs_qualified(PRV_S);

‎riscv/insns/sfence_vma.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('S');
2-
require_impl(IMPL_MMU);
2+
require(p->has_mmu());
33
if (STATE.v) {
44
if (STATE.prv == PRV_U || get_field(STATE.hstatus->read(), HSTATUS_VTVM))
55
require_novirt();

‎riscv/isa_parser.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -114,12 +114,6 @@ typedef enum {
114114
} isa_extension_t;
115115

116116
typedef enum {
117-
IMPL_MMU_SV32,
118-
IMPL_MMU_SV39,
119-
IMPL_MMU_SV48,
120-
IMPL_MMU_SV57,
121-
IMPL_MMU_SBARE,
122-
IMPL_MMU,
123117
IMPL_MMU_VMID,
124118
IMPL_MMU_ASID,
125119
} impl_extension_t;

‎riscv/processor.cc‎

Lines changed: 16 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -67,11 +67,7 @@ processor_t::processor_t(const char* isa_str, const char* priv_str,
6767
set_pmp_granularity(cfg->pmpgranularity);
6868
set_pmp_num(cfg->pmpregions);
6969

70-
if (isa.get_max_xlen() == 32)
71-
set_mmu_capability(IMPL_MMU_SV32);
72-
else if (isa.get_max_xlen() == 64)
73-
set_mmu_capability(IMPL_MMU_SV57);
74-
70+
set_max_vaddr_bits(0);
7571
set_impl(IMPL_MMU_ASID, true);
7672
set_impl(IMPL_MMU_VMID, true);
7773

@@ -217,31 +213,26 @@ void processor_t::set_pmp_granularity(reg_t gran)
217213
lg_pmp_granularity = ctz(gran);
218214
}
219215

220-
void processor_t::set_mmu_capability(int cap)
216+
void processor_t::set_max_vaddr_bits(unsigned n)
221217
{
222-
switch (cap) {
223-
case IMPL_MMU_SV32:
224-
set_impl(IMPL_MMU_SV32, true);
225-
set_impl(IMPL_MMU, true);
218+
switch (n) {
219+
case 0:
226220
break;
227-
case IMPL_MMU_SV57:
228-
set_impl(IMPL_MMU_SV57, true);
229-
[[fallthrough]];
230-
case IMPL_MMU_SV48:
231-
set_impl(IMPL_MMU_SV48, true);
232-
[[fallthrough]];
233-
case IMPL_MMU_SV39:
234-
set_impl(IMPL_MMU_SV39, true);
235-
set_impl(IMPL_MMU, true);
221+
case 32:
222+
if (isa.get_max_xlen() != 32)
223+
abort();
236224
break;
237-
default:
238-
set_impl(IMPL_MMU_SV32, false);
239-
set_impl(IMPL_MMU_SV39, false);
240-
set_impl(IMPL_MMU_SV48, false);
241-
set_impl(IMPL_MMU_SV57, false);
242-
set_impl(IMPL_MMU, false);
225+
case 39:
226+
case 48:
227+
case 57:
228+
if (isa.get_max_xlen() != 64)
229+
abort();
243230
break;
231+
default:
232+
abort();
244233
}
234+
235+
max_vaddr_bits = n;
245236
}
246237

247238
reg_t processor_t::select_an_interrupt_with_default_priority(reg_t enabled_interrupts) const

‎riscv/processor.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,9 @@ class processor_t : public abstract_device_t
290290
extension_enable_table[ext] = enable && isa.extension_enabled(ext);
291291
}
292292
void set_impl(uint8_t impl, bool val) { impl_table[impl] = val; }
293+
bool has_mmu() const { return max_vaddr_bits != 0; }
294+
unsigned get_max_vaddr_bits() const { return max_vaddr_bits; }
295+
void set_max_vaddr_bits(unsigned);
293296
bool supports_impl(uint8_t impl) const {
294297
return impl_table[impl];
295298
}
@@ -358,6 +361,7 @@ class processor_t : public abstract_device_t
358361
state_t state;
359362
uint32_t id;
360363
unsigned xlen;
364+
unsigned max_vaddr_bits;
361365
bool histogram_enabled;
362366
bool log_commits_enabled;
363367
FILE *log_file;

‎riscv/sim.cc‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -214,16 +214,16 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
214214
// handle mmu-type
215215
const char *mmu_type;
216216
rc = fdt_parse_mmu_type(fdt, cpu_offset, &mmu_type);
217+
procs[cpu_idx]->set_max_vaddr_bits(0);
217218
if (rc == 0) {
218-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SBARE);
219219
if (strncmp(mmu_type, "riscv,sv32", strlen("riscv,sv32")) == 0) {
220-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV32);
220+
procs[cpu_idx]->set_max_vaddr_bits(32);
221221
} else if (strncmp(mmu_type, "riscv,sv39", strlen("riscv,sv39")) == 0) {
222-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV39);
222+
procs[cpu_idx]->set_max_vaddr_bits(39);
223223
} else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) {
224-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV48);
224+
procs[cpu_idx]->set_max_vaddr_bits(48);
225225
} else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) {
226-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV57);
226+
procs[cpu_idx]->set_max_vaddr_bits(57);
227227
} else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) {
228228
// has been set in the beginning
229229
} else {
@@ -233,8 +233,6 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
233233
<< mmu_type << ").\n";
234234
exit(1);
235235
}
236-
} else {
237-
procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SBARE);
238236
}
239237

240238
procs[cpu_idx]->reset();

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