Greatly simplify instruction decoding

The opcode map was complex and fairly inefficient.  Using a simple search
is easier to understand and actually works faster in practice.
Heuristically speeding up the search by occasionally resorting helps even
further.

Author: aswaterman

riscv/processor.cc

@@ -662,31 +662,38 @@ reg_t processor_t::throw_instruction_address_misaligned(reg_t pc)
 
 insn_func_t processor_t::decode_insn(insn_t insn)
 {
-  if (!extension_enabled(EXT_ZCA) && insn_length(insn.bits()) % 4)
-    return &::illegal_instruction;
+  bool rve = extension_enabled('E');
 
-  // look up opcode in hash table
-  size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
-  auto [hit, desc] = opcode_cache[idx].lookup(insn.bits());
+  if (unlikely(!extension_enabled(EXT_ZCA) && insn_length(insn.bits()) % 4))
+    return &::illegal_instruction;
 
-  bool rve = extension_enabled('E');
+  auto& oc = opcode_cache[insn.bits() % std::size(opcode_cache)];
+  if (likely(oc[0].first->matches(insn.bits())))
+    return oc[0].first->func(xlen, rve, log_commits_enabled);
+
+  // linearly search the opcode cache
+  for (size_t i = 1; i < oc.size(); i++) {
+    auto desc = oc[i].first;
+    if (desc->matches(insn.bits())) {
+      oc[i].second++;
+
+      // periodically sort the opcode cache in descending order of frequency
+      if (unlikely(--opcode_cache_sort_count == 0)) {
+        opcode_cache_sort_count = OPCODE_CACHE_SORT_COUNT;
+
+        for (auto& oc : opcode_cache) {
+          std::stable_sort(oc.begin(), oc.end(), [](auto a, auto b) {
+            if (a.first->overlap || b.first->overlap)
+              return false;
+            return a.second > b.second;
+          });
+        }
+      }
 
-  if (unlikely(!hit)) {
-    // fall back to linear search
-    auto matching = [insn_bits = insn.bits()](const insn_desc_t &d) {
-      return (insn_bits & d.mask) == d.match;
-    };
-    auto p = std::find_if(custom_instructions.begin(),
-                          custom_instructions.end(), matching);
-    if (p == custom_instructions.end()) {
-      p = std::find_if(instructions.begin(), instructions.end(), matching);
-      assert(p != instructions.end());
+      return desc->func(xlen, rve, log_commits_enabled);
     }
-    desc = &*p;
-    opcode_cache[idx].replace(insn.bits(), desc);
   }
-
-  return desc->func(xlen, rve, log_commits_enabled);
+  return &::illegal_instruction;
 }
 
 void processor_t::register_insn(insn_desc_t desc, bool is_custom) {
@@ -701,8 +708,25 @@ void processor_t::register_insn(insn_desc_t desc, bool is_custom) {
 
 void processor_t::build_opcode_map()
 {
-  for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
-    opcode_cache[i].reset();
+  const insn_bits_t N = std::size(opcode_cache);
+
+  auto insert = [&](auto& insn) {
+    auto stride = std::min(N, insn_bits_t(1) << ctz(~insn.mask));
+
+    for (size_t i = insn.match & (stride - 1); i < N; i += stride)
+      if ((insn.match % N) == (i & insn.mask))
+        opcode_cache[i].push_back({&insn, 0});
+  };
+
+  for (size_t i = 0; i < N; i++)
+    opcode_cache[i].clear();
+
+  std::for_each(custom_instructions.begin(), custom_instructions.end(), insert);
+  std::for_each(instructions.begin(), instructions.end(), insert);
+
+  for (size_t i = 0; i < N; i++)
+    if (opcode_cache[i].empty())
+      opcode_cache[i].push_back({&insn_desc_t::illegal_instruction, 0});
 }
 
 void processor_t::register_extension(extension_t *x) {
@@ -752,7 +776,8 @@ void processor_t::register_base_instructions()
       logged_rv32i_##name, \
       logged_rv64i_##name, \
       logged_rv32e_##name, \
-      logged_rv64e_##name \
+      logged_rv64e_##name, \
+      name##_overlapping \
     }; \
     register_base_insn(insn); \
   }
@@ -775,9 +800,6 @@ void processor_t::register_base_instructions()
   #undef DEFINE_INSN
   #undef DEFINE_INSN_UNCOND
 
-  // terminate instruction list with a catch-all
-  register_base_insn(insn_desc_t::illegal_instruction);
-
   build_opcode_map();
 }
 

riscv/processor.h

@@ -43,6 +43,12 @@ struct insn_desc_t
   insn_func_t logged_rv64i;
   insn_func_t logged_rv32e;
   insn_func_t logged_rv64e;
+  bool overlap = true;
+
+  bool matches(insn_bits_t insn) const
+  {
+    return (insn & mask) == match;
+  }
 
   insn_func_t func(int xlen, bool rve, bool logged) const
   {
@@ -207,47 +213,6 @@ struct state_t
   void csr_init(processor_t* const proc, reg_t max_isa);
 };
 
-class opcode_cache_entry_t {
- public:
-  opcode_cache_entry_t()
-  {
-    reset();
-  }
-
-  void reset()
-  {
-    for (size_t i = 0; i < associativity; i++) {
-      tag[i] = 0;
-      contents[i] = &insn_desc_t::illegal_instruction;
-    }
-  }
-
-  void replace(insn_bits_t opcode, const insn_desc_t* desc)
-  {
-    for (size_t i = associativity - 1; i > 0; i--) {
-      tag[i] = tag[i-1];
-      contents[i] = contents[i-1];
-    }
-
-    tag[0] = opcode;
-    contents[0] = desc;
-  }
-
-  std::tuple<bool, const insn_desc_t*> lookup(insn_bits_t opcode)
-  {
-    for (size_t i = 0; i < associativity; i++)
-      if (tag[i] == opcode)
-        return std::tuple(true, contents[i]);
-
-    return std::tuple(false, nullptr);
-  }
-
- private:
-  static const size_t associativity = 4;
-  insn_bits_t tag[associativity];
-  const insn_desc_t* contents[associativity];
-};
-
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
@@ -409,8 +374,9 @@ class processor_t : public abstract_device_t
   std::vector<insn_desc_t> custom_instructions;
   std::unordered_map<reg_t,uint64_t> pc_histogram;
 
-  static const size_t OPCODE_CACHE_SIZE = 4095;
-  opcode_cache_entry_t opcode_cache[OPCODE_CACHE_SIZE];
+  static const size_t OPCODE_CACHE_SORT_COUNT = 5000000;
+  size_t opcode_cache_sort_count = OPCODE_CACHE_SORT_COUNT;
+  std::vector<std::pair<const insn_desc_t*, reg_t>> opcode_cache[128];
 
   void take_pending_interrupt() { take_interrupt(state.mip->read() & state.mie->read()); }
   void take_interrupt(reg_t mask); // take first enabled interrupt in mask