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kseniadobrovolskayakseniadobrovolskaya
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Added a custom plugin to execute any code after each instruction
 Added extensions to implement: 1. Mask agnostic behavior of filling with 1s - xspikema1s 2. Tail agnostic behavior of filling with 1s - xspiketa1s
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9 files changed

+704
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‎ci-tests/spike-ld.ld‎

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ENTRY (_entry)
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SECTIONS {
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. = 0x80000000;
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.text : { *(.text) }
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.data : { *(.data) }
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}
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‎ci-tests/test-spike‎

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@@ -26,6 +26,7 @@ riscv64-linux-gnu-gcc -static -O2 -o hello $CI/hello.c
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riscv64-linux-gnu-gcc -static -O2 -o dummy-slliuw $CI/dummy-slliuw.c
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riscv64-linux-gnu-gcc -static -O2 -o customcsr $CI/customcsr.c
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riscv64-linux-gnu-gcc -static -O2 -o atomics $CI/atomics.c
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riscv64-linux-gnu-gcc -static -nostdlib -o test-spiketama1s-ext -O0 -march=rv64gcv -mabi=lp64d -T $CI/spike-ld.ld $CI/test-spiketama1s-ext.S
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# run snippy-based tests
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wget https://github.com/syntacore/snippy/releases/download/snippy-2.1/snippy-x86_64-linux.tar.xz
@@ -46,6 +47,45 @@ g++ -std=c++2a -I$INSTALL/include -L$INSTALL/lib $CI/testlib.cc -lriscv -o /dev/
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# run tests
4748
time $INSTALL/bin/spike --isa=rv64gc $BUILD/pk/pk hello | grep "Hello, world! Pi is approximately 3.141588."
4849
$INSTALL/bin/spike --log-commits --isa=rv64gc $BUILD/pk/pk atomics 2> /dev/null | grep "First atomic counter is 1000, second is 100"
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$INSTALL/bin/spike -l --log-commits --isa=rv64gcv_xspikema1s_xspiketa1s test-spiketama1s-ext &> spike-all-fill1s.log
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grep "v2 0x00000000ffffffffffffffff00000002" spike-all-fill1s.log
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grep "v3 0xffffffff000000000000000000000003" spike-all-fill1s.log
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grep "v4 0xffffffffffffffffffffffffff000000" spike-all-fill1s.log
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grep "v5 0xffffffffffffffffffffffffffffc000" spike-all-fill1s.log
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! grep "v6 0x" spike-all-fill1s.log
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grep "v7 0xffffffffffffffff00000000ffff0000" spike-all-fill1s.log
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grep "v8 0xffffffffffffffffffffffffffff0000" spike-all-fill1s.log
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grep "v9 0xffffffffffffffffffffffffff410113" spike-all-fill1s.log
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grep "v10 0xffffffffffff000002b1048700000113" spike-all-fill1s.log
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grep "v11 0xffffffffffffffffffffffffffffffff" spike-all-fill1s.log
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grep "v12 0xffffffff02b10487000000000c410113" spike-all-fill1s.log
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grep "v13 0xffffffffffffffffffffffffffffffff" spike-all-fill1s.log
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grep "v14 0x0c4101130c410113000000000c410113" spike-all-fill1s.log
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grep "v15 0xffffffffffffffff000000000c410113" spike-all-fill1s.log
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grep "v16 0xffffffffffffffffffff000000000000" spike-all-fill1s.log
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grep "v17 0xffffffffffffffffffffffffffffffff" spike-all-fill1s.log
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grep "v18 0xffffffffffffffffffffffffffffffff" spike-all-fill1s.log
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grep "v19 0xffffffffffffffffffffffffffffffff" spike-all-fill1s.log
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grep "v20 0xffffffff000000000206205700000113" spike-all-fill1s.log
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grep "v21 0xffffffff0000000055076e0000000c41" spike-all-fill1s.log
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grep "v22 0xffffffff000000000001b05700000487" spike-all-fill1s.log
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grep "v24 0xffffffffffffffffffffffffff000000" spike-all-fill1s.log
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grep "v25 0xffffffffffffffffffffffffff000000" spike-all-fill1s.log
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grep "v26 0xffff000000000000f557b05700000113" spike-all-fill1s.log
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grep "v27 0xffff000000000000cc81020600000c41" spike-all-fill1s.log
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grep "v28 0xffff0000000000000213550700000487" spike-all-fill1s.log
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grep "v29 0xffff00000000000000200001000002b1" spike-all-fill1s.log
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grep "v30 0xffffffffffffffff000000000c410113" spike-all-fill1s.log
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grep "v31 0xffffffffffffffff0000000002b10487" spike-all-fill1s.log
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$INSTALL/bin/spike -l --log-commits --isa=rv64gcv_xspikema1s test-spiketama1s-ext &> spike-mask-fill1s.log
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grep "v2 0x00000000ffffffffffffffff00000002" spike-mask-fill1s.log
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grep "v3 0x00000000000000000000000000000003" spike-mask-fill1s.log
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$INSTALL/bin/spike -l --log-commits --isa=rv64gcv_xspiketa1s test-spiketama1s-ext &> spike-tail-fill1s.log
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grep "v2 0x00000000000000000000000000000002" spike-tail-fill1s.log
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grep "v3 0xffffffff000000000000000000000003" spike-tail-fill1s.log
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$INSTALL/bin/spike -l --log-commits --isa=rv64gcv test-spiketama1s-ext &> spike-undisturbed.log
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grep "v2 0x00000000000000000000000000000002" spike-undisturbed.log
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grep "v3 0x00000000000000000000000000000003" spike-undisturbed.log
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LD_LIBRARY_PATH=$INSTALL/lib ./test-libriscv $BUILD/pk/pk hello | grep "Hello, world! Pi is approximately 3.141588."
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LD_LIBRARY_PATH=$INSTALL/lib ./test-customext $BUILD/pk/pk dummy-slliuw | grep "Executed successfully"
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LD_LIBRARY_PATH=$INSTALL/lib ./test-custom-csr $BUILD/pk/pk customcsr | grep "Executed successfully"

‎ci-tests/test-spiketama1s-ext.S‎

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.option norvc
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.global _entry
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.global fromhost
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.global tohost
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.text
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_entry:
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la t0, exception_handler
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csrw mtvec, t0
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csrr t1, mstatus
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// Setting bit number 9 (mstatus.VS)
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li t2, 1
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slli t2, t2, 9
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or t1, t1, t2
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// Setting bit number 13 (mstatus.FS)
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li t3, 1
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slli t3, t3, 13
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or t1, t1, t3
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csrw mstatus, t1
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//----------------------------MASK AGNOSTIC TEST-------------------------------
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// Tail undisturbed, mask agnostic with VL = 3
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vsetivli a0, 3, e32, m1, tu, ma
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vmclr.m v0
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// Mask v0 - 0x00000000000000010000000100000001
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vadd.vi v0, v0, 1
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// Fourth element should be zero because of tu
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// If mask fill 1s extension (xspikema1s) enable:
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// Second and third elements should be 0xffffffff because of 0001 mask
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// v2 0x00000000ffffffffffffffff00000002
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// If mask fill 1s extension (xspikema1s) disable:
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// Second and third elements should be zero because of 0001 mask
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// v2 0x00000000000000000000000000000002
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vadd.vi v2, v2, 2, v0.t
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//----------------------------TAIL AGNOSTIC TEST-------------------------------
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vsetivli a0, 3, e32, m1, ta, mu
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// Second and third elements should be zero because of 0001 mask with mu
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// If tail fill 1s extension (xspiketa1s) enable:
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// Fourth element should be 0xffffffff because of ta
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// v3 0xffffffff000000000000000000000003
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// If tail fill 1s extension (xspiketa1s) disable:
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// Fourth element should be zero because of ta
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// v3 0x00000000000000000000000000000003
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vadd.vi v3, v3, 3, v0.t
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//-----------------------------VCOMPRESS.VM TEST-------------------------------
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// Tail agnostic, mask undisturbed with VL = 8
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vsetivli a0, 8, e8, m1, ta, mu
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vmclr.m v0
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vadd.vi v0, v0, 13
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// Mask v0 - 0b...00001101 => 3 setting bits (of the first 8) => 3 elements
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// packed, remaining elements - tail: v4 0xffffffffffffffffffffffffff000000
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vcompress.vm v4, v1, v0
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//-----------------------------MASK LOGICAL TEST-------------------------------
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// Tail undisturbed, mask agnostic with VL = 14
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vsetivli a0, 14, e8, m1, tu, ma
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// Mask destination => unmasked, tail-agnostic
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// v5 0xffffffffffffffffffffffffffffc000
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vmand.mm v5, v5, v5
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//--------------------------SCALAR DESTINATION TEST----------------------------
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vsetivli a0, 8, e8, m1, ta, ma
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// t1 = x6, check that v6 hasn't been changed
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vcpop.m t1, v1, v0.t
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//-------------------------------VIOTA.M TEST----------------------------------
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// Tail agnostic, mask agnostic with VL = 5
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vsetivli a0, 5, e16, m1, ta, ma
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vmclr.m v0
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vadd.vi v0, v0, 13
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// Mask v0 - 0b...00001101
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// packed, remaining elements - tail: v7 0xffffffffffffffff00000000ffff0000
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viota.m v7, v1, v0.t
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//--------------------------------VMV.S.X TEST---------------------------------
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// Only first element updated, remaining elements - tail:
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// v8 0xffffffffffffffffffffffffffff0000
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vmv.s.x v8, sp
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//---------------------------------VLM.V TEST----------------------------------
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// Tail agnostic, mask agnostic with VL = 31
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vsetivli a0, 31, e32, m8, tu, ma
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// For all loads, we will use this address of the executable section (so that
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// the bytes are unambiguous) placed in the sp.
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li sp, 0x00000000800000c4
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// Destination register is always written with a tail-agnostic policy.
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// evl = ceil(vl / 8) = 3, eew = 8 => tail starts from third element
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// v9 0xffffffffffffffffffffffffff410113
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vlm.v v9, 0(sp)
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//--------------------------VECTOR UNIT-STRIDE TEST----------------------------
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// Tail agnostic, mask agnostic with VL = 5
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vsetivli a0, 5, e8, m1, ta, ma
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vmclr.m v0
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vadd.vi v0, v0, 13
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// Mask v0 - 0b...00001101
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// Masked vector loads do not update inactive elements.
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// eew = 16, sew = 8 ignored.
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// v10 0xffffffffffff000002b1048700000113
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// v11 0xffffffffffffffffffffffffffffffff
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vle16.v v10, 0(sp), v0.t
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//----------------------------VECTOR STRIDED TEST------------------------------
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// Tail agnostic, mask agnostic with VL = 3
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vsetivli a0, 3, e16, m1, ta, ma
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// Mask v0 - 0b...00001101
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li tp, 2
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// Masked vector loads do not update inactive elements.
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// eew = 32, sew = 16 ignored.
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// v12 0xffffffff02b10487000000000c410113
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// v13 0xffffffffffffffffffffffffffffffff
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vlse32.v v12, 0(sp), tp, v0.t
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//----------------------------VECTOR INDEXED TEST------------------------------
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// Tail agnostic, mask agnostic with VL = 6
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vsetivli a0, 6, e32, m2, ta, ma
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// Mask v0 - 0b...00011101
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li tp, 29
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vmv.s.x v0, tp
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// Masked vector loads do not update inactive elements.
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// eew = sew = 32
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// v14 0x0c4101130c410113000000000c410113
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// v15 0xffffffffffffffff000000000c410113
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vloxei8.v v14, 0(sp), v1, v0.t
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//------------------VECTOR UNIT-STRIDE FAULT-ONLY-FIRST TEST-------------------
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// Tail agnostic, mask agnostic with VL = 31
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vsetivli a0, 31, e8, m2, ta, ma
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// Mask v0 - 0b...001111
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li tp, 15
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// For all fault-only-first loads, we will use this address, because a few
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// bytes after it (0x00000000ffffffff), a trap happens.
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vmv.s.x v0, tp
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li tp, 0x00000000fffffffa
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// Load instructions may overwrite active destination vector register group
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// elements past the element index at which the trap is reported.
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// Here element with index 3 raised an exception => vl reduced to 3.
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// eew = 16, sew = 8 ignored.
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// v16 0xffffffffffffffffffff000000000000
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// v17 0xffffffffffffffffffffffffffffffff
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// v18 0xffffffffffffffffffffffffffffffff
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// v19 0xffffffffffffffffffffffffffffffff
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vle16ff.v v16, (tp), v0.t
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//----------------------VECTOR UNIT-STRIDE SEGMENT TEST------------------------
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// Tail agnostic, mask agnostic with VL = 6
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vsetivli a0, 6, e32, m2, ta, ma
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// Mask v0 - 0b...0001101
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li t0, 13
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vmv.s.x v0, t0
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// Masked vector loads do not update inactive elements.
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// nf = 3
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// v20 0xffffffff000000000206205700000113
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// v21 0xffffffff0000000055076e0000000c41
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// v22 0xffffffff000000000001b05700000487
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vlseg3e16.v v20, 0(sp), v0.t
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//-------------VECTOR UNIT-STRIDE SEGMENT FAULT-ONLY-FIRST TEST----------------
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// Tail agnostic, mask agnostic with VL = 14
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vsetivli a0, 14, e8, m1, ta, ma
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// nf = 2, vl reduced to 3.
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// v24 0xffffffffffffffffffffffffff000000
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// v25 0xffffffffffffffffffffffffff000000
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vlseg2e8ff.v v24, (tp), v0.t
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//------------------------VECTOR STRIDED SEGMENT TEST--------------------------
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// Tail agnostic, mask agnostic with VL = 7
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vsetivli a0, 7, e32, m2, ta, ma
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// Mask v0 - 0b...0001101
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// Masked vector loads do not update inactive elements.
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li t1, 8
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// nf = 4
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// v26 0xffff000000000000f557b05700000113
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// v27 0xffff000000000000cc81020600000c41
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// v28 0xffff0000000000000213550700000487
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// v29 0xffff00000000000000200001000002b1
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vlsseg4e16.v v26, 0(sp), t1, v0.t
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182+
//------------------------VECTOR INDEXED SEGMENT TEST--------------------------
183+
// Tail agnostic, mask agnostic with VL = 2
184+
vsetivli a0, 2, e32, m1, ta, ma
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// Mask v0 - 0b...00001
186+
vmclr.m v0
187+
vadd.vi v0, v0, 1
188+
// Masked vector loads do not update inactive elements.
189+
// v30 0xffffffffffffffff000000000c410113
190+
// v31 0xffffffffffffffff0000000002b10487
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vluxseg2ei32.v v30, 0(sp), v1, v0.t
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//---------------------------------END TESTING---------------------------------
194+
la t0, exit
195+
jalr t0
196+
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exception_handler:
198+
csrr x10, mcause
199+
// In case of breakpoint (Interrupt = 0, Exception code = 3) we finalize.
200+
// Otherwise it's not the expected behavior and we go into an infinite loop.
201+
li x11, 3
202+
beq x10, x11, exit
203+
j infinite_loop
204+
205+
exit:
206+
li ra, 1
207+
la sp, tohost
208+
sd ra, 0(sp)
209+
210+
infinite_loop:
211+
j infinite_loop
212+
213+
.balign 64
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tohost:
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.8byte 0x0
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.balign 64
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fromhost:
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.8byte 0x0

‎customext/agnostic_macros.h‎

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#ifndef _RISCV_AGNOSTIC_MACROS_H
2+
#define _RISCV_AGNOSTIC_MACROS_H
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4+
#include "decode_macros.h"
5+
#include "insn_macros.h"
6+
7+
#include <cassert>
8+
9+
#define AGNOSTIC_RVV_PARAMS \
10+
reg_t UNUSED vl = P.VU.vl->read(); \
11+
reg_t UNUSED vstart = P.VU.vstart->read(); \
12+
reg_t UNUSED sew = P.VU.vsew; \
13+
reg_t rd_num_start = insn.rd(); \
14+
reg_t rd_num = rd_num_start;
15+
16+
#define AGNOSTIC_VD_PARAM(x) \
17+
type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
18+
type_usew_t<x>::type all_ones = -1;
19+
20+
#define AGNOSTIC_SEW_SWITCH(BODY) \
21+
do { \
22+
if (sew == e8) { \
23+
AGNOSTIC_VD_PARAM(e8); \
24+
BODY; \
25+
} else if (sew == e16) { \
26+
AGNOSTIC_VD_PARAM(e16); \
27+
BODY; \
28+
} else if (sew == e32) { \
29+
AGNOSTIC_VD_PARAM(e32); \
30+
BODY; \
31+
} else if (sew == e64) { \
32+
AGNOSTIC_VD_PARAM(e64); \
33+
BODY; \
34+
} \
35+
} while (0)
36+
37+
#define AGNOSTIC_LOOP_TAIL(BODY, TAIL_FROM, TAIL_TO) \
38+
do { \
39+
AGNOSTIC_RVV_PARAMS; \
40+
for (reg_t i = (TAIL_FROM); i < (TAIL_TO); ++i) { \
41+
AGNOSTIC_SEW_SWITCH(BODY); \
42+
} \
43+
} while (0)
44+
45+
#define AGNOSTIC_LOOP_BODY(BODY) AGNOSTIC_LOOP_TAIL(BODY, vstart, vl)
46+
47+
#define AGNOSTIC_LOOP_MASK_TAIL(VALUE, TAIL_FROM, TAIL_TO) \
48+
do { \
49+
AGNOSTIC_RVV_PARAMS; \
50+
for (reg_t i = (TAIL_FROM); i < (TAIL_TO); ++i) \
51+
P.VU.set_mask_elt(rd_num, i, (VALUE)); \
52+
} while (0)
53+
54+
#define AGNOSTIC_LOOP_LOAD_TAIL(BODY, EEW, NF, TAIL_FROM, TAIL_TO) \
55+
do { \
56+
AGNOSTIC_RVV_PARAMS; \
57+
sew = (EEW); \
58+
for (; rd_num < rd_num_start + (NF); ++rd_num) { \
59+
for (reg_t i = (TAIL_FROM); i < (TAIL_TO); ++i) { \
60+
AGNOSTIC_SEW_SWITCH(BODY); \
61+
} \
62+
} \
63+
} while (0)
64+
65+
inline bool is_rvv_or_fp_store(insn_t insn) {
66+
// rvv-spec-1.0: Vector Load/Store Instruction Encoding: unit-stride,
67+
// strided, indexed stores.
68+
// FP stores also have this opcode.
69+
return insn.opcode() == 0b0100111;
70+
}
71+
72+
inline bool is_rvv_or_fp_load(insn_t insn) {
73+
// rvv-spec-1.0: Vector Load/Store Instruction Encoding: unit-stride,
74+
// strided, indexed loads.
75+
// FP loads also have this opcode.
76+
return insn.opcode() == 0b0000111;
77+
}
78+
79+
inline bool is_rvv([[maybe_unused]] insn_t insn) {
80+
const auto &opcode = insn.opcode();
81+
const auto &bits = insn.bits();
82+
if (is_rvv_or_fp_load(insn)) {
83+
return (bits & MASK_FLD) != MATCH_FLD && (bits & MASK_FLH) != MATCH_FLH &&
84+
(bits & MASK_FLQ) != MATCH_FLQ && (bits & MASK_FLW) != MATCH_FLW;
85+
}
86+
if (is_rvv_or_fp_store(insn)) {
87+
return (bits & MASK_FSD) != MATCH_FSD && (bits & MASK_FSH) != MATCH_FSH &&
88+
(bits & MASK_FSQ) != MATCH_FSQ && (bits & MASK_FSW) != MATCH_FSW;
89+
}
90+
return opcode == 0b1010111 || opcode == 0b1110111;
91+
}
92+
93+
inline bool is_rvv_scalar_dest(insn_t insn) {
94+
assert(is_rvv(insn));
95+
const auto &bits = insn.bits();
96+
return (bits & MASK_VSETVL) == MATCH_VSETVL ||
97+
(bits & MASK_VSETVLI) == MATCH_VSETVLI ||
98+
(bits & MASK_VSETIVLI) == MATCH_VSETIVLI ||
99+
(bits & MASK_VCPOP_M) == MATCH_VCPOP_M ||
100+
(bits & MASK_VFIRST_M) == MATCH_VFIRST_M ||
101+
(bits & MASK_VMV_X_S) == MATCH_VMV_X_S ||
102+
(bits & MASK_VFMV_F_S) == MATCH_VFMV_F_S;
103+
}
104+
105+
#endif

‎customext/customext.mk.in‎

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@@ -7,5 +7,7 @@ customext_subproject_deps = \
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customext_srcs = \
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dummy_rocc.cc \
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cflush.cc \
10+
spikema1s.cc \
11+
spiketa1s.cc \
1012

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customext_install_shared_lib = yes

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