Does 'V' imply 'F" and "D' ?

[chihminchao]

riscv-isa-sim/disasm/isa_parser.cc

Line 101 in 8df626b

[[fallthrough]];

based on https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#183-v-vector-extension-for-application-processors
"The V extension depends upon the F and D extensions, and implements all vector floating-point instructions (Section Vector Floating-Point Instructions) for floating-point operands with EEW=32 or EEW=64 (including widening instructions and conversions between FP32 and FP64). Vector single-width floating-point reductions (Vector Single-Width Floating-Point Reduction Instructions) for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64."

Should it be dependent but not implied ?

[aswaterman]

I would say that clarifying this distinction is an outstanding issue for the ISA spec authors to resolve. But in my mind, there is essentially no difference between “depends on” and “implies”. We can get rid of the error-checking code and treat “depends on” as “implies” if we are so inclined. cc @kasanovic

…

On Mon, Oct 13, 2025 at 9:41 PM Chih-Min Chao ***@***.***> wrote: *chihminchao* created an issue (riscv-software-src/riscv-isa-sim#2104) <#2104> https://github.com/riscv-software-src/riscv-isa-sim/blob/8df626bf1dd88750ebc3e2121c36b92f6fc0db86/disasm/isa_parser.cc#L101 based on https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#183-v-vector-extension-for-application-processors "The V extension depends upon the F and D extensions, and implements all vector floating-point instructions (Section Vector Floating-Point Instructions <https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-float>) for floating-point operands with EEW=32 or EEW=64 (including widening instructions and conversions between FP32 and FP64). Vector single-width floating-point reductions (Vector Single-Width Floating-Point Reduction Instructions <https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-float-reduce>) for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64." Should it be dependent but not implied ? — Reply to this email directly, view it on GitHub <#2104>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAH3XQUSYV2UOUB7FVAKTAD3XR5GZAVCNFSM6AAAAACJDIWYAGVHI2DSMVQWIX3LMV43ASLTON2WKOZTGUYTEMZTGEZDCOA> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[mslijepc]

@aswaterman I have a question similar to this one - if V implies D, is this isa string correct?

rv64imafcv_zba_zbb_zcb_zcmp_zcmt...

Because I get an error

Zcmp' and 'Zcmt' extensions are incompatible with 'Zcd' extension

(and the reason is

riscv-isa-sim/disasm/isa_parser.cc

Line 466 in 217cbc5

if (extension_table['D'])

)

[aswaterman]

Spike is correct here: V implies D, and C + D implies Zcd, which is incompatible with Zcmt.

The fix is to remove C from the string and use Zca instead.